0-9999计数器程序

2、0-9999计数器的低层设计（VHDL语言代码）分频器程序：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitydivisgeneric(n:integer:=50000000);port(clk:instd_logic;q:outstd_logic);enddiv;architecturebhvofdivissignalcount:integerrangen-1downto0:=n-1;beginprocess(clk)beginifclk'eventandclk='1'andclk'last_value='0'thencount=count-1;ifcount=n/2thenq='0';elseq='1';endif;ifcount=0thencount=n-1;endif;endif;endprocess;end;计数器程序：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycnt_10isport(clk,en,reset:instd_logic;cnt1,cnt2:outstd_logic_vector(3downto0));end;architecturebhvofcnt_10issignaltemp1,temp2:std_logic_vector(3downto0);signalc:std_logic;begincnt1=temp1;cnt2=temp2;p1:process(clk,reset)beginifreset='1'thentemp1=0000;elsifclk'eventandclk='1'thenifen='1'theniftemp11001thentemp1=temp1+1;c='0';elsetemp1=0000;c='1';endif;endif;endif;endprocessp1;p2:process(reset,c)beginifreset='1'thentemp2=0000;elsifc'eventandc='1'thenifen='1'theniftemp21001thentemp2=temp2+1;elsetemp2=0000;endif;endif;endif;endprocessp2;end;数码管显示程序：libraryieee;useieee.std_logic_1164.all;entitydisplayisport(clk_s:instd_logic;data1,data2:instd_logic_vector(3downto0);dig:outstd_logic_vector(1downto0);seg:outstd_logic_vector(7downto0));end;architecturebhvofdisplayissignalcnt:std_logic;signald:std_logic_vector(3downto0);beginp0:process(clk_s)beginifclk_s'eventandclk_s='1'thencnt=notcnt;endif;endprocessp0;p1:process(cnt)begincasecntiswhen'0'=dig=10;d=data1;when'1'=dig=01;d=data2;endcase;endprocessp1;p2:process(d)begincasediswhen0000=seg=11000000;when0001=seg=11111001;when0010=seg=10100100;when0011=seg=10110000;when0100=seg=10011001;when0101=seg=10010010;when0110=seg=10000010;when0111=seg=11111000;when1000=seg=10000000;when1001=seg=10010000;whenothers=seg=11111111;endcase;endprocessp2;end;