AT89C51 DATASHEET

1PQFP/TQFP12345678910113332313029282726252423P1.5P1.6P1.7RST(RXD)P3.0NC(TXD)P3.1(INT0)P3.2(INT1)P3.3(T0)P3.4(T1)P3.5PO.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPNCALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)44434241403938373635341213141516171819202122(WR)P3.6(RD)P3.7XTAL2XTAL1GNDGND(A8)P2.0(A9)P2.1(A10)P2.2(A11)P2.3(A12)P2.4P1.4P1.3P1.2P1.1(T2EX)P1.0(T2)NCVCCP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)Features•CompatiblewithMCS-51™Products4KBytesofIn-SystemReprogrammableFlashMemory–Endurance:1,000Write/EraseCyclesFullyStaticOperation:0Hzto24MHzThree-levelProgramMemoryLock128x8-bitInternalRAM32ProgrammableI/OLinesTwo16-bitTimer/CountersSixInterruptSourcesProgrammableSerialChannelLow-powerIdleandPower-downModesDescriptionTheAT89C51isalow-power,high-performanceCMOS8-bitmicrocomputerwith4KbytesofFlashprogrammableanderasablereadonlymemory(PEROM).ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindustry-standardMCS-51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconven-tionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithFlashonamonolithicchip,theAtmelAT89C51isapowerfulmicrocomputerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.PDIP12345678910111213141516171819204039383736353433323130292827262524232221P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST(RXD)P3.0(TXD)P3.1(INT0)P3.2(INT1)P3.3(T0)P3.4(T1)P3.5(WR)P3.6(RD)P3.7XTAL2XTAL1GNDVCCP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)Rev.0265G–02/008-bitMicrocontrollerwith4KBytesFlashAT89C51NotRecommendedforNewDesigns.UseAT89S51.PinConfigurationsPLCC78910111213141516173938373635343332313029P1.5P1.6P1.7RST(RXD)P3.0NC(TXD)P3.1(INT0)P3.2(INT1)P3.3(T0)P3.4(T1)P3.5PO.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPNCALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)65432144434241401819202122232425262728(WR)P3.6(RD)P3.7XTAL2XTAL1GNDNC(A8)P2.0(A9)P2.1(A10)P2.2(A11)P2.3(A12)P2.4P1.4P1.3P1.2P1.1P1.0NCVCCP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)AT89C512BlockDiagramPORT2DRIVERSPORT2LATCHP2.0-P2.7FLASHPORT0LATCHRAMPROGRAMADDRESSREGISTERBUFFERPCINCREMENTERPROGRAMCOUNTERDPTRRAMADDR.REGISTERINSTRUCTIONREGISTERBREGISTERINTERRUPT,SERIALPORT,ANDTIMERBLOCKSSTACKPOINTERACCTMP2TMP1ALUPSWTIMINGANDCONTROLPORT3LATCHPORT3DRIVERSP3.0-P3.7PORT1LATCHPORT1DRIVERSP1.0-P1.7OSCGNDVCCPSENALE/PROGEA/VPPRSTPORT0DRIVERSP0.0-P0.7AT89C513TheAT89C51providesthefollowingstandardfeatures:4KbytesofFlash,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillatorandclockcir-cuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsystemtocontinuefunctioning.ThePower-downModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset.PinDescriptionVCCSupplyvoltage.GNDGround.Port0Port0isan8-bitopen-drainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0mayalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalpro-gramanddatamemory.InthismodeP0hasinternalpullups.Port0alsoreceivesthecodebytesduringFlashprogram-ming,andoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.Port1Port1isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.Port2Port2isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,itusesstronginternalpullupswhenemitting1s.Duringaccessestoexternaldatamem-orythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.Port3Port3isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepullups.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelow