VHDL程序

全加器实验代码：libraryieee;useieee.std_logic_1164.all;entityF_ADDER1isport(a,b,c:instd_logic;ci,si:outstd_logic);endentityF_ADDER1;architectureactofF_ADDER1issignalt:std_logic_vector(2downto0);begint=c&b&a;process(a,b,c)begincasetiswhen000=si='0';ci='0';when001=si='1';ci='0';when010=si='1';ci='0';when011=si='0';ci='1';when100=si='1';ci='0';when101=si='0';ci='1';when110=si='0';ci='1';when111=si='1';ci='1';whenothers=null;endcase;endprocess;endarchitectureact;architectureact1ofF_ADDER1issignalt:std_logic_vector(2downto0);begint=c&b&a;process(a,b,c)beginift=000thensi='0';ci='0';elsift=001thensi='1';ci='0';elsift=010thensi='1';ci='0';elsift=011thensi='0';ci='1';elsift=100thensi='1';ci='0';elsift=101thensi='0';ci='1';elsift=110thensi='0';ci='1';elsift=111thensi='1';ci='1';elsenull;endif;endprocess;endarchitectureact1;architectureact2ofF_ADDER1issignalt:std_logic_vector(2downto0);signaly:std_logic_vector(1downto0);begint=c&b&a;y=00whent=000ELSE01whent=001ELSE01whent=010ELSE10whent=011ELSE01whent=100ELSE10whent=101ELSE10whent=110ELSE11whent=111;ci=y(1);si=y(0);endarchitectureact2;architectureact3ofF_ADDER1issignalt:std_logic_vector(2downto0);signaly:std_logic_vector(1downto0);begint=c&b&a;withtselecty=00when000,01when001,01when010,10when011,01when100,10when101,10when110,11whenothers;ci=y(1);si=y(0);endarchitectureact3;architectureact4ofF_ADDER1isbeginci=(aandb)or(aandc)or(bandc);si=axorbxorc;endarchitectureact4;configurationsmall_countofF_ADDER1isforactendfor;endsmall_count;交通灯代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitytraffic_lightisport(clk,ret:instd_logic;Q:outstd_logic_vector(11downto0);shuma1,shuma0:outstd_logic_vector(6downto0));endtraffic_light;architectureactoftraffic_lightiscomponentdevide50port(clkin:instd_logic;clk_div:outstd_logic);endcomponent;typetrafficis(s1,s2,s3,s4);signalcs:traffic:=s1;signalcnt:integerrange3downto0;--黄灯signalcnt1:integerrange35downto0;--记录南北signalcnt2:integerrange60downto0;--记录东西signalnet1:std_logic;beginu1:devide50portmap(clkin=clk,clk_div=net1);process(net1,ret)beginif(ret='1')thencnt1=35;cnt2=0;cnt=0;cs=s1;elsif(rising_edge(net1))thencasecsiswhens1=if(cnt1/=1)thencnt1=cnt1-1;elsecs=s2;cnt=3;endif;whens2=if(cnt/=1)thencnt=cnt-1;elsecs=s3;cnt2=60;endif;whens3=if(cnt2/=1)thencnt2=cnt2-1;elsecs=s4;cnt=3;endif;whens4=if(cnt/=1)thencnt=cnt-1;elsecs=s1;cnt1=35;endif;whenothers=NULL;endcase;endif;endprocess;process(cs,cnt,cnt1,cnt2)variableshi,ge:integerrange0to9;begincasecsiswhens1=Q=100001100001;shi:=cnt1/10;ge:=cnt1rem10;whens2=Q=100010100010;shi:=cnt/10;ge:=cntrem10;whens3=Q=001100001100;shi:=cnt2/10;ge:=cnt2rem10;whens4=Q=010100010100;shi:=cnt/10;ge:=cntrem10;whenothers=Q=000000000000;endcase;casegeiswhen0=shuma0=1000000;when1=shuma0=1111001;when2=shuma0=0100100;when3=shuma0=0110000;when4=shuma0=0011001;when5=shuma0=0010010;when6=shuma0=0000010;when7=shuma0=1111000;when8=shuma0=0000000;when9=shuma0=0010000;whenothers=shuma0=1111111;endcase;caseshiiswhen0=shuma1=1000000;when1=shuma1=1111001;when2=shuma1=0100100;when3=shuma1=0110000;when4=shuma1=0011001;when5=shuma1=0010010;when6=shuma1=0000010;when7=shuma1=1111000;when8=shuma1=0000000;when9=shuma1=0010000;whenothers=shuma1=1111111;endcase;endprocess;endact;数字钟实验代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityclockisport(clk,ch,cm,cs:instd_logic;buz:bufferstd_logic;Q5,Q4,Q3,Q2,Q1,Q0:outstd_logic_vector(6downto0));endclock;architectureactofclockiscomponentdevide50port(clkin:instd_logic;clk_div:outstd_logic);endcomponent;componentdevide_1kHzport(clk_in:instd_logic;clk_out:outstd_logic);endcomponent;signalnet1,net2:std_logic;signalsec:integerrange0to59;signalmin:integerrange0to59;signalhour:integerrange0to23;signaltmp:bit:='0';--状态记录beginu1:devide50portmap(clkin=clk,clk_div=net1);u2:devide_1kHzportmap(clk_in=clk,clk_out=net2);process(net1,cs,ch,cm)beginif(cs='0')thentmp='0';sec=0;elsif(rising_edge(net1))thenif(cm='0')thenif(min59)thenmin=min+1;elsemin=0;endif;elsif(ch='0')thenif(hour23)thenhour=hour+1;elsehour=0;endif;elsetmp='1';if(sec59)thensec=sec+1;elsesec=0;if(min59)thenmin=min+1;elsemin=0;if(hour23)thenhour=hour+1;elsehour=0;endif;endif;endif;endif;endif;endprocess;process(net2,sec,min,cs,cm,ch)variablet:std_logic;begint:=csandcmandch;if(t='1'andtmp='1')thenif(min=59)thenif(sec=50andsec=58andsecrem2=0)thenif(rising_edge(net2))thenbuz=notbuz;--500Hzendif;endif;elsif(min=0)thenif(sec=0)thenbuz=net2;--1KHzendif;endif;endif;endprocess;process(sec)variableshi,ge:integerrange0to9;beginshi:=sec/10;ge:=secrem10;casegeiswhen0=Q0=1000000;when1=Q0=1111001;when2=Q0=0100100;when3=Q0=0110000;when4=Q0=0011001;when5=Q0=0010010;when6=Q0=0000010;when7=Q0=1111000;when8=Q0=0000000;when9=Q0=0010000;whenothers=Q0=1111111;endcase;caseshiiswhen0=Q1=1000000;when