Self-timed Architecture for Masked Successive Appr

Self-timedArchitectureforMaskedSuccessiveApproximationAnalog-to-DigitalConversionTaskinKocak,GeorgeR.HarrisandRonaldF.DeMaraSchoolofElectricalEngineeringandComputerScienceUniversityofCentralFlorida,Orlando,Florida32816-2450E-mail:[e-mail];tel:[phone];fax:[phone]AbstractInthispaper,anovelarchitectureforself-timedanalog-to-digitalconversionispresented,designedusingtheNULLConventionLogic(NCL)paradigm.Thisanalog-to-digitalcon-verter(ADC)employssuccessiveapproximationandaone-hotencodedmaskingtechniquetodigitizeanalogsignals.Thearchitecturescalesreadilytoanygivenresolutionbyutilizingtheone-hotencodedschemetopermitidenticallogicalcomponentsforeachbitofresolution.The4-bitconfigurationoftheproposeddesignhasbeenimplementedandassessedviasim-ulationin0.18-µmCMOStechnology.Furthermore,theADCmaybeinterfacedwitheithersynchronousorfour-phaseasynchronousdigitalsystems.Keywords:Asynchronousdigitalsystems,self-timeddesigns,analog-to-digitalconversion,nullconventionlogic,successiveapproximation.1IntroductionTheneedforhighperformance,lowpower,andlowelectromagneticinterference(EMI)analog-to-digitalconverters(ADCs)hasledresearcherstoconsiderasynchronousapproachesasalter-nativestoconventionalclockeddesigns.Amotivatingfactorhasbeenthatasclockfrequen-ciesincrease,sodocomplicationsregardingtheclockseffectsonEMI,powerdissipation,andaverage-caseperformance[18,21,22].Inaddition,clocktransitionsfacilitatethesimultaneousoccurrenceofmultipleswitchingevents.Thisresultsinmaximumtaxationofthesupplyrailsatnearlyidenticaltimeintervalscreatingapower-railgroupingeffect.Unfortunately,thismaycorruptsensitiveanaloginputsignalsastheyarebeingsampled,andconsequentlyleadtoinac-curateconversions.Whilethebenefitsofasynchronousdesignhavebeendemonstratedindigitallogiccircuits[15],weinvestigateherenovelmeansbywhichtheseadvantagescanbecarriedoverintothemixed-signaldomain.Asynchronouscircuitsfallintotwomaincategories:self-timedandbounded-delaymod-els.NCLassumesdelaysinbothlogiccircuitsandinterconnectstobeunbounded.Ontheotherhand,well-knownmethodssuchasHuffmancircuits[10],burst-modecircuits[11]andmi-cropipelines[12]assumethatdelaysinbothgatesandwiresarebounded.Delaysareaddedbasedonworst-casescenariostoavoidhazardconditions.Thisleadstoextensivetiminganalysisofworst-casebehaviortoensurecorrectcircuitoperation[9].Self-timeddesignshavedemonstratedhigherapplication-levelthroughputsinceaveragecasedelayislessthanthatofsynchronouscir-cuitswhicharedesignedtoaccomodatetheworst-casepropagationdelays[18][19].Duetoeliminationofclocktreestheyhavedemonstratedreducepowerconsumption[20][22].AlsoimportantforADCapplications,NCLandotherself-timedcircuitshaveshownreducedElec-tromagneticInterferenceeffectsandnoiseduetotheirinherentlynon-synchronizedswitchingcharacteristics[21][22].AdesignconsiderationistheincreasedarearequiredwhenusingNCL,whichisapproximately1.5to2timesasmuchastheequivalentsynchronousdesign.However,forlargedesigns,suchasSoCs,theprocessorcore(s)normallyrequire(s)lessthanhalfofthechip’stotalarea.Therefore,theincreasedareafortheNCLimplementationoftheprocessorcore(s)islesssignificant,especiallyconsideringtheincreasedrobustnessandnumerousotheradvantages.Forexample,theinitialversionoftheMotorolaHCS08processorimplementedintheNCLparadigm(theNCL08)andfabricatedusingstaticCMOSgateswitha0.25-µmprocess,showsa40%reductioninpoweranda10dBreductioninpeaknoiseoveritsclockedBooleancounterpart,whileoperatingatacomparablethroughput[22].ThestateofasynchronousADCdesignisstillinitsinfancy,withrelativelyfewdesignsbeingformallypresented[1,2,3,4].Todate,existingdesignshavedemonstratedcomparableorfasteraverageconversiontimeswhenevaluatedagainstsynchronousconverters.Theyhavealsodemonstratedvariousmeansofachievingmetastability-freeconversionunderlowpowerandlownoiseconstraints.Inspiteofthepotentialadvantagesofasynchronousconversionapproaches,afundamentalquestionarises.Thatiswhetherasynchronousconvertersthatshowtemporallyindeterministicnaturecanworkinreal-timeapplications,whichrequireconversionswithinafixedtimeinterval.2However,itispossibletoguaranteeanasynchronousconvertercancompleteoperationswithinatimebound[2],butthesecircuitsreintroducetheneedforstringenttiminganalysissimilartothatfoundinclockedsystems.Unboundeddelayconverterssuchastheonespresentedinthispapercandeliverpredictablemaximumandaverageconversionrates,butdonotguaranteeaminimumrate.Nonetheless,theminimumachievedratesforsynchronousconvertersremaininfluencedbyphysicaloperatingconditionsinasimilarmanner.Inthefollowingsections,anoverviewofNULLConventionLogic(NCL)isfirstpresented,asitisusedtorealizethedigitallogicfunctionsintheADC.Next,theproposedarchitectureoftheself-timedsuccessiveapproximation(SA)ADCisdescribed,independentofresolution,withdiscussionsonboththedigitalandanalogfunctions.The4-bitconfigurationoftheADCarchitectureisthensimulatedinSPICEusingCadencedesigntoolsanda0.18-µmCMOStechnologylibrary.Thesimulationresultsandtheirimplicationsaresubsequentlydiscussed.2NULLConventionLogic(NCL)NULLConventionLogic(NCL)isaself-timedl