CY2305_08中文资料

CY2305CY2309Low-Cost3.3VZeroDelayBufferCypressSemiconductorCorporation•198ChampionCourt•SanJose,CA95134-1709•408-943-2600Document#:38-07140Rev.*IRevisedSeptember18,2008Features■10MHzto100-/133MHzoperatingrange,compatiblewithCPUandPCIbusfrequencies■Zeroinput-outputpropagationdelay■60pstypicalcycle-to-cyclejitter(highdrive)■Multiplelow-skewoutputs❐85pstypicaloutput-to-outputskew❐Oneinputdrivesfiveoutputs(CY2305)❐Oneinputdrivesnineoutputs,groupedas4+4+1(CY2309)■CompatiblewithPentium-basedsystems■TestModetobypassphase-lockedloop(PLL)(CY2309only[see“SelectInputDecoding”onpage3])■Availableinspace-saving16-pin150-milSOICor4.4-mmTSSOPpackages(CY2309),and8-pin,150-milSOICpackage(CY2305)■3.3Voperation■IndustrialtemperatureavailableFunctionalDescriptionTheCY2309isalow-cost3.3Vzerodelaybufferdesignedtodistributehigh-speedclocksandisavailableina16-pinSOICorTSSOPpackage.TheCY2305isan8-pinversionoftheCY2309.Itacceptsonereferenceinput,anddrivesoutfivelow-skewclocks.The-1Hversionsofeachdeviceoperateatupto100-/133MHzfrequencies,andhavehigherdrivethanthe-1devices.Allpartshaveon-chipPLLswhichlocktoaninputclockontheREFpin.ThePLLfeedbackison-chipandisobtainedfromtheCLKOUTpad.TheCY2309hastwobanksoffouroutputseach,whichcanbecontrolledbytheSelectinputsasshowninthe“SelectInputDecoding”tableonpage3.Ifalloutputclocksarenotrequired,BankBcanbethree-stated.Theselectinputsalsoallowtheinputclocktobedirectlyappliedtotheoutputsforchipandsystemtestingpurposes.TheCY2305andCY2309PLLsenterapowerdownmodewhentherearenorisingedgesontheREFinput.Inthisstate,theoutputsarethree-statedandthePLListurnedoff,resultinginlessthan25.0μAcurrentdrawfortheseparts.TheCY2309PLLshutsdowninoneadditionalcaseasshowninthetablebelow.MultipleCY2305andCY2309devicescanacceptthesameinputclockanddistributeit.Inthiscase,theskewbetweentheoutputsoftwodevicesisguaranteedtobelessthan700ps.TheCY2305/CY2309isavailableintwo/threedifferentconfigurations,asshownintheorderinginformation(page10).TheCY2305-1/CY2309-1isthebasepart.TheCY2305-1H/CY2309-1Histhehigh-driveversionofthe-1,anditsriseandfalltimesaremuchfasterthanthe-1s.LogicBlockDiagramPLLMUXSelectInputREFS2S1CLKA1CLKA2CLKA3CLKA4CLKB1CLKB2CLKB3CLKB4DecodingCLKOUT[+]FeedbackCY2305CY2309Document#:38-07140Rev.*IPage2of15PinoutsFigure1.PinDiagram-CY2305Figure2.PinDiagram-CY2309Table1.PinDescriptionforCY2305PinSignalDescription1REF[1]Inputreferencefrequency,5V-tolerantinput2CLK2[2]Bufferedclockoutput3CLK1[2]Bufferedclockoutput4GNDGround5CLK3[2]Bufferedclockoutput6VDD3.3Vsupply7CLK4[2]Bufferedclockoutput8CLKOUT[2]Bufferedclockoutput,internalfeedbackonthispinTable2.PinDescriptionforCY2309PinSignalDescription1REF[1]Inputreferencefrequency,5V-tolerantinput2CLKA1[2]Bufferedclockoutput,BankA3CLKA2[2]Bufferedclockoutput,BankA4VDD3.3Vsupply5GNDGround6CLKB1[2]Bufferedclockoutput,BankB7CLKB2[2]Bufferedclockoutput,BankB8S2[3]Selectinput,bit29S1[3]Selectinput,bit110CLKB3[2]Bufferedclockoutput,BankB11CLKB4[2]Bufferedclockoutput,BankB12GNDGround12345876REFCLK2CLK1GNDVDDCLKOUTCLK4CLK312345678910111213141516REFCLKA1CLKA2VDDGNDCLKB1CLKB2S2CLKOUTCLKA4CLKA3VDDGNDCLKB4CLKB3S1Notes1.Weakpulldown.2.Weakpulldownonalloutputs.3.Weakpullupsontheseinputs.[+]FeedbackCY2305CY2309Document#:38-07140Rev.*IPage3of15Figure3.REF.InputtoCLKA/CLKBDelayvs.LoadingDifferencebetweenCLKOUTandCLKA/CLKBPinsZeroDelayandSkewControlAlloutputsmustbeuniformlyloadedtoachieveZeroDelaybetweentheinputandoutput.SincetheCLKOUTpinistheinternalfeedbacktothePLL,itsrelativeloadingcanadjusttheinput-outputdelay.Thisisshownintheabovegraph.Forapplicationsrequiringzeroinput-outputdelay,alloutputs,includingCLKOUT,mustbeequallyloaded.EvenifCLKOUTisnotused,itmusthaveacapacitiveload,equaltothatonotheroutputs,forobtainingzeroinput-outputdelay.Ifinputtooutputdelayadjustmentsarerequired,usetheabovegraphtocalculateloadingdifferencesbetweentheCLKOUTpinandotheroutputs.Forzerooutput-outputskew,besuretoloadalloutputsequally.Forfurtherinformationrefertotheapplicationnoteentitled“CY2305andCY2309asPCIandSDRAMBuffers.”13VDD3.3Vsupply14CLKA3[2]Bufferedclockoutput,BankA15CLKA4[2]Bufferedclockoutput,BankA16CLKOUT[2]Bufferedoutput,internalfeedbackonthispinSelectInputDecodingforCY2309S2S1CLOCKA1–A4CLOCKB1–B4CLKOUT[4]OutputSourcePLLShutdown00Three-stateThree-stateDrivenPLLN01DrivenThree-stateDrivenPLLN10DrivenDrivenDrivenReferenceY11DrivenDrivenDrivenPLLNTable2.PinDescriptionforCY2309PinSignalDescriptionNotes4.ThisoutputisdrivenandhasaninternalfeedbackforthePLL.Theloadonthisoutputcanbeadjustedtochangetheskewbetweenthereferenceandoutput.[+]FeedbackCY2305CY2309Document#:38-07140Rev.*IPage4of15AbsoluteMaximumConditionsSupplyVoltagetoGroundPotential................–0.5Vto+7.0VDCInputVoltage(ExceptREF)............–0.5VtoVDD+0.5VDCInputVoltageREF.........................................–0.5Vto7VStorageTemperature.................................–65°Cto+150°CJunctionTemperature.................................................150°CStaticDischargeVoltage(perMIL-STD-883,Method3015)...........................2,000VOperatingCondit