WAT 电性参数介绍(WAT Parameters introduction)

1WATParametersReviewSpeaker:AlanHuang2FlowWhyWAT?WATParameterReview.1)ProcesstestMethodology.2)DevicetestMethodology.3)ProcessFactorInfluenceonWATPara.WATApplication1)GeneralGuide-linewhenWATfail2)Exampleintroduce3WhyWAT?DebugtheProcessError.MonitorProcessWindow.CheckDesignRule.ControltheProcessParameters(SPC).ReliabilityCharacterization.DeviceModelingforCircuitDesign.DevelopnextGeneration.4(in=13206.24614.8)TST2TST1TST7TST3TST4TST8TST9TST5TST6(out=13326.24734.8)(0.0)frame=120x120TestsiteandTestlinelocation5DeviceCategorizationActiveDeviceMOSFET(N/P),FieldTransistor,BJT,DiodePassiveDeviceResistor,CapacitorsDesignrulesIsolation,lines(Spacing,Continuity)contact,extensionResistor1)DiffusionregionsN+,N-,P+,N-Well,P-Well,Deep-NW2)ThinfilmsP1,P2,M1,M2,M33)Contact:C3toN+/P+,ViaC3toP1,P26WATParameterReviewProcessPart:1)Spacing(Bridge,short)2)Continuity(Open)3)Isolation4)SheetRs5)ContactRc6)KelvinStructureforResistance7)Integrity(Interlayerdielectric)8)Extensionrulecheck9)CDmeasurement10)JunctionleakageDevicePart:1)Gm(Vth,CurrentGain)2)Idsat(Asym)3)Ioff4)Swing5)Gammafactor6)BKV7)Isub8)Leff,Rext,Weff9)FieldDevicetest10)Capacitance7ProcessPart:(1)Spacing(Bridge,short)Define：验证在Process中，同层/同层之间的隔绝能力!Measurementmethod：Force1uA电流到导线上，假若线路中有short，则测量出的电压值就偏低(7volt.需注意此Structure之bottomlayer可垫其它layers,以模拟不同topography下Photo.&Etching的能力！Pad1Pad2Spacing:(P1,P2,M1,M2,M3)Width:(P1,P2,M1,M2,M3)8ProcessPart:(2)Continuity(Open)Continuity的值可反映出Metal,Poly1orPoly2CD的控制能力！一般来说，此项参数要与Spacing要同时来看，如此才能判定Layer的status是否正常！Pad1Pad2Spacing:(P1,P2,M1,M2,M3)Width:(P1,P2,M1,M2,M3)9ProcessPart:(3)IsolationDefine：验证在Process中，两不同层之间的隔绝能力！PS：此Pattern要注意,若oxidationquality太差,亦会影响到P1/C3是否short的误判Isolationexample：P1/C3,P2/C3,P1/P2,M1/M2…PAAC3M1Poly1PAA外框P+IM,P-IMNW外框PFIM10ProcessPart:(4)Sheet（薄层电阻Rs）Define：因厚度测量不易，故Define之σ=1/ρ=nqμR=V/I=ρ(L/WT)=(ρ/T)x(L/W)Rs=ρ/T=Rx(W/L)PS：σ(Conductivity传导系数)；ρ(Resistivity电阻率)；μ(mobility迁移率)；n(concentration浓度)；T(thickness厚度)；NAAPWC3NAAM1C3M1Poly2N+IMPN-IMPPWPoly111ProcessPart:(5)Contact（接触电阻）RcDefine：利用Chain的结构,将contact的阻值以Patterndesign的方式模拟出实际的contactRc大小！PS：(1)RcNormalize后的大小，往往会失真，故当个数过多时，不建议Normalize！(2)以patterndesign而言,有垫其它layer（如右下)的Structure在CMP的process中已失去参考价值了！M2M2M1ViaM2M20.4651.251.15M2P1P2M212ProcessPart:(6)KelvinStructureforResistanceDefine：以ForceCurrentthenSenseVoltagedrop的方式,测量低阻值的导线或Contact的四端电阻测量法！PS：一般来说在Req50的结构中,ForceI=0.01uAandVoltagelim=10V!(Req=L/W)Pad1Pad2Pad3Pad41um15um70um2um(W)70um1000L13ProcessPart:(7)Integrity(Gate-Oxide-Integrity)Define:验证Gateoxide的Quality好坏之一项参数当Gateoxideuniformity不均,或Interface间有defects时,会形成一漏电流路径失去OxideIsolation的能力！Measurementmethod:一般测量法不外乎ForceV/IandmeasureI/V1.ForceVandmeasureI:SweepVoltonPolygate,andVb=groundthenmeasureIg(about~pA),IfIgincreaseto1uA,thisSweepVoltisBKV(normallarge7V)2.ForceIandmeasureV:Force1uAonPolygatethenmeasureVoltagePS:测量方式取决于Patterndesign(commonpadissue)WELLPolyGate14ProcessPart:(8)ExtensionrulecheckDefine：以sense漏电流的方式，测量Contactoverlay的Designrulecheck!PS：(1)一般来说，layout的结构会采用十字架的形式，最大的好处是在把shotissues的问题抓出!!(2)miss-align与contactnumber无关！M2ViaM1M1exttovia用Poly4垫15ProcessPart:(9)CDmeasurementDefine:籍由测量两条同长度，不同宽度的电阻，换算出其宽度CD大小！PS:当W=W1时可测量得电阻R1W=W2时可测量得电阻R2R1=Rs*L/(W1-ΔW)R2=Rs*L/(W2-ΔW)R1/R2=(W2-ΔW)/(W1-ΔW)则ΔW(CDloss),Rs皆可求得！(P1CD大小影响到Channellength的长短,需特别注意）16ProcessPart:(10)JunctionleakageDefine：一般来说leakage指的是反向偏压时的漏电流测量，通常有以下三种分类：1.Contactleak2.Dielectricleak(usuallyforDRAM)3.Junctionleak(bulkorperi)PS:I-bulk(meas)=A-bulk*J-area(current/um2)+L-peri*J-peri(current/um)I-finger(meas)=A-fing*J-area(current/um2)+L-peri(current/um)(J-area,J-peri可求）PW拉出NAA有打BlanketN+impN-impC3M117DevicePart:1)Gm(Vth,CurrentGain)Define:Gm=(ΔId/ΔVg)a)Linear:Id=1/2(μCoxW/L)(2(Vgs-Vt)Vds-Vds2)Gm=μCoxW/Lμb)Saturation:Id=1/2(μCoxW/L)(Vgs-Vt)2Gm=μCoxW/L(Vgs-Vt)c)Pinch-Off:Vds=Vgs-VtGm=μCox(W/L)Vdsβ=μCox(W/L)PS:Ifβvalueabnormal,ItmayhaveGox,Lefforimplantissues.VthMeasuremethod:Step1:Vds=0.1Vs=Vb=0andswoopVgStep2:PlotIdsVgsandGmVgscurvesStep3:findGm(max),plotslopofthispointonIdsVgsFromLinearfunctionsetId=0thenVth=Vgs-V03VgId18DevicePart:2)Idsat(Asym)Define:Idsat=IdsatVgs=Vds=VccIdsMeasuremethod:Step1:Vs=Vb=0,Vd=VccandSweepVgStep2:PlotIdsVgsStep3:FindIdsatVg=Vd=VccIdsAsymmetrycheck:Step1:FollowingtheIdsmeasurement.Step2:ChangeDrainandSourcePin-assign,thenmeasureIds’.Step3:Asym=ABS(Ids-Ids’)/IdsPS:IfIdsAsymmetryAvnormal,ItmayhavetheIsub,(orPolygatenon-overlapissues)orLDDN-Rs,orContactRcsomethingstrouble!ASMU2VgGDSSubVsubSMU3IdVdSMU119DevicePart:3)IoffDefine:Ids=IoffatVgs=Vs=Vb=0,Vds=VccIoffMeasuremethod(Directmeas.):Step1:Vs=Vb=0,Vd=VccandSweepVgStep2:PlotIdsVgsStop3:FindIdsatVg=0Ps:测量机台的灵敏度，须注意与曲线的相关联性！IoffMeasuremethod(外插法):Step1:FollowtheIoffDirectmeas.methodStep2:PlotMaxslopofthiscurveonlog(Ids)VgsStep3:FindtheIdsatVg=0intercept.logIdVgVd=VcclogIdVgVd=Vcc20DevicePart:4)Swing(SubthresholdSlop,St)Define:Swing=(Δlog(Ids)/ΔVgs)-1=2(kt/q)(1+Cd/Cox)**当Vg逐渐增加,channelaccumulationdeplationweakinversionstronginversion,Swing既是测量weakinversion时Id与Vg的变化程度!!(exponential)DIBleffectme