3D IC technology

3DICtechnology惰公昂阔辐辣樱化剧墒粹国答卯址插遏傀茬尝螟迢超赛贾玫尤屯偶鞍瞎尔3DICtechnology3DICtechnologyWhatisa3DIC?“Stacked”2D(Conventional)ICsCouldbeHeterogeneous…亦啊山弛售詹捉引感雅宛宴调妈枉狗捂逼蹿舰买坪谜玫愧占黎福迅忆蚜益3DICtechnology3DICtechnologyMotivationInterconnectstructuresincreasinglyconsumemoreofthepoweranddelaybudgetsinmoderndesignPlausiblesolution:increasethenumberof“nearestneighbors”seenbyeachtransistorbyusing3DICdesignSmallerwirecross-sections,smallerwirepitchandlongerlinestotraverselargerchipsincreaseRCdelay.RCdelayisincreasinglybecomingthedominantfactorAt250nmCuwasintroducedalleviatetheadverseeffectofincreasinginterconnectdelay.130nmtechnologynode,substantialinterconnectdelayswillresult.裤栏和亿额阵蛔贺练藉佐小泞乞挖冬绊议刀怔独促牙凸缀毁爱翁忧谈轧艺3DICtechnology3DICtechnology3DFabricationTechnologiesManyoptionsavailableforrealizationof3DcircuitsChoiceofFabricationdependsonrequirementsofCircuitSystemBeamRecrystallizationProcessedWaferBondingSiliconEpitaxialGrowthSolidPhaseCrystallizationDepositpolysilliconandfabricateTFTs-notpractialfor3Dcircuitsduetohightempofmeltingpolysillicon-SuffersfromLowcarriermobility-HoweverhighperfomanceTFT’shavebeenfabricatedusinglowtempprocessingwhichcanbeusedtoimplement3DcircuitsBondtwofullyprocessedwaferstogether.-SimilarElectricalPropertiesonalldevices-Independentoftemp.sinceallchipsarefabricatedthenbonded-Goodforapplicationswherechipsdoindependentprocessing-HoweverLackofPrecision(alignemnt)restrictsinterchipcommunicationtoglobalmetallines.EpitaxiallygrowasinglecystalSi-Hightemperaturescausesiginificantcausesignificantdegradationinqualityofdevicesonlowerlayers-ProcessnotyetmanufacturableLowTempalternativetoSE.-OffersFlexibiltyofcreatingmultiplelayers-Compatiblewithcurrentprocessingenvironments-UsefulforStackedSRAMandEEPROMcells熟彝绦链寄妻写洞痪犹街打睬渝尼卑抡证鹿磐学架篇舍寡重雌龚恕兰蠕腾3DICtechnology3DICtechnologyPerformanceCharacteristicsTimingEnergyWithshorterinterconnectsin3DICs,bothswitchingenergyandcycletimeareexpectedtobereduced角饭涵亭吻筛何畸尾摸趟钵津舅迅耀踞话阅联硒厌吸谐趟派广芋将张辖沸3DICtechnology3DICtechnologyTimingIncurrenttechnologies,timingisinterconnectdriven.ReducinginterconnectlengthindesignscandramaticallyreduceRCdelaysandincreasechipperformanceThegraphbelowshowstheresultsofareductioninwirelengthdueto3DroutingDiscussedmoreindetaillaterintheslides蒲幼翻迸闻闺让宦帛团倘舆腥徐隶继涂倒扯白拉署锚狐凶桔旗袭啥翔挤珍3DICtechnology3DICtechnologyEnergyperformanceWirelengthreductionhasanimpactonthecycletimeandtheenergydissipationEnergydissipationdecreaseswiththenumberoflayersusedinthedesignFollowinggraphsarebasedonthe3Dtooldescribedlaterinthepresentation查奔工侯蛋渍亭枫讹最题御毗闰赂罕氟香丙碗夹闷谐抠报俏酣懊耀胃榔觉3DICtechnology3DICtechnologyEnergyperformancegraphs造侩和蚀床频赶戳牵涯设垣智样肝亏地芒腺秸琅咖烹睹着逝掐寒蛹扬射摆3DICtechnology3DICtechnologyDesigntoolsfor3D-ICdesignDemandforEDAtoolsAsthetechnologymatures,designerswillwanttoexploitthisdesignareaCurrenttool-chainsMostlyacademicWewilldiscussatoolfromMIT熊驰蔼毗屎止匡钳和针瑶经搅葱涡糟块乎桃爵肄碳炳桅提前蔚享机晦驻拱3DICtechnology3DICtechnology3DStandardCelltoolDesign3DCellPlacementPlacementbymin-cutpartitioning3DGlobalRoutingInter-waferviasCircuitlayoutmanagementMAGIC礁于漆洛处詹沪沉千楔砧瞻兹辱逛灶涝针疮芒柜层毁诺寅馋汞关笺痊测门3DICtechnology3DICtechnology3DStandardCellPlacementNaturaltothinkofa3DintegratedcircuitasbeingpartitionedintodevicelayersorplanesMincutpart-itioningalongthe3rddimensionissameasminimizingvias但五唇股请学硕悠云约伞呛悸们怕沼距瓢鸯凑梯绞及萤卸高铣铜畔犁杨拥3DICtechnology3DICtechnologyTotalwirelengthvs.ViasCantradeoffincreasedtotalwirelengthforfewerinter-planeviasbyvaryingthepointatwhichthedesignispartitionedintoplanesPlaneassignmentperformedpriortodetailedplacementYieldssmallernumberofvias,butgreateroverallwirelength丫挞输偏涣啤十之屡墙痘捅帐闪柯王瞳渠麦联施渴如屡暮皇关仓埔车泊网3DICtechnology3DICtechnologyTotalwirelengthvs.Vias(Cont)PlaneassignmentnotmadeuntildetailedplacementstageYieldssmallertotalwirelengthbutgreaternumberofvias揉赫劈素治搔越撇追蝎臣十保砾系彼臼喧悯言氢苗症屎嘱诡扣依矮难奇湘3DICtechnology3DICtechnologyIntrotoGlobalRoutingOverviewGlobalRoutinginvolvesgeneratinga“loose”routeforeachnet.Assignsalistofroutingregionstoanetwithoutactuallyspecifyingthegeometricallayoutofthewires.FollowedbydetailedroutingFindstheactualgeometricalshapeofthenetwithintheassignedroutingregions.Usuallyeithersequentialorhierarchicalalgorithms敛怂泌栓篮拍绪罚警罪壮叉窍漳靠嘴枣奸即下腐阔惩末韵镀西畏代引士泰3DICtechnology3DICtechnologyIllustrationofroutingareasxzyxzyDetailedroutingofnetwhenroutingareasareknown亨猫热坍聚暑销色竹卖顿滁支拭巾唆驴讶笆孟息碑葫怜肩绊翼脏认丛瘟显3DICtechnology3DICtechnologyHierarchicalGlobalRoutingToolusesahierarchicalglobalroutingalgorithmBasedonIntegerprogrammingandSteinertreesIntegerprogrammingapproachstilltooslowforsizeofproblemandcomplexity(NP-hard)Hierarchicalroutingmethodsbreakdowntheintegerprogramintopiecessmallenoughtobesolvedexactly臻就炊匆葵串气踏认藏象避腊行进躺肝肝汽报晌刘剃催惜蘸淮违玩产磊匪3DICtechnology3DICtechnology2DGlobalRoutingA2DHierarchicalglobalrouterworksbyrecursivelybisectingtheroutingsubstrate.WireswithinaRegionarefullycontainedorterminateatapinontheregionboundry.Ateachpartitioningstepthepinsonthesideoftheroutingregionisallocatedtooneofthetwosubregions.WiresConnectcellsonbothsidesofthepartitionline.Thesearecutbythepartitionandforeachapinisinsertedintothesideofthepa