TI RM48Lx30安全系统MCU解决方案

TIRM48Lx30安全系统MCU解决方案关键字：工业控制,安全系统,PLC,工厂自动化,机器人TI公司的RM48Lx30是高性能安全系统用的微控制器(MCU),它的安全架构包括两个步调一致的CPU,CPU和存储器内置自测(BIST)逻辑,闪存和数据SRAM的ECC,效率高达1.6DMIPS/MHz的ARM®Cortex™-R4F浮点CPU,并可配置到在200MHz运行,提供高达320DMIPS,支持little-endian[LE32]格式,主要用在工业安全系统如工业自动化,安全PLC,电源产生和分布,电梯以及医疗电子如呼吸机,心脏除颤器,输液泵和胰岛素泵,放射疗法和手术机器人等.本文介绍了RM48Lx30主要特性,功能方框图和RM48Hercules™ARM®SafetyMCU开发套件(HDK)主要特性,方框图与电路图.TheRM48Lx30isahighperformancemicrocontrollerfamilyforsafetysystems.ThesafetyarchitectureincludesDualCPUsinlockstep,CPUandMemoryBuilt-InSelfTest(BIST)logic,ECConboththeFlashandthedataSRAM,parityonperipheralmemories,andloopbackcapabilityonperipheralIOs.TheRM48Lx30integratestheARM®Cortex™-R4FFloatingPointCPUwhichoffersanefficient1.6DMIPS/MHz,andhasconfigurationswhichcanrunupto200MHzprovidingupto320DMIPS.Thedevicesupportsthelittle-endian[LE32]format.TheRM48Lx30hasupto3MBintegratedFlashandupto256KBdataRAMconfigurationswithsinglebiterrorcorrectionanddoublebiterrordetection.Theflashmemoryonthisdeviceisanonvolatile,electricallyerasableandprogrammablememoryimplementedwitha64-bit-widedatabusinterface.Theflashoperatesona3.3Vsupplyinput(samelevelasI/Osupply)forallread,programanderaseoperations.Wheninpipelinemode,theflashoperateswithasystemclockfrequencyofupto200MHz.TheSRAMsupportssingle-cycleread/writeaccessesinbyte,halfword,andwordmodes.TheRM48Lx30devicefeaturesperipheralsforreal-timecontrol-basedapplications,includingtwoNextGenerationHighEndTimer(N2HET)timingcoprocessorswithupto44totalIOterminalsanda12-bitAnalog-to-Digitalconvertersupportingupto24inputs.TheN2HETisanadvancedintelligenttimerthatprovidessophisticatedtimingfunctionsforreal-timeapplications.Thetimerissoftware-controlled,usingareducedinstructionset,withaspecializedtimermicromachineandanattachedI/Oport.TheN2HETcanbeusedforpulsewidthmodulatedoutputs,captureorcompareinputs,orgeneral-purposeI/O.Itisespeciallywellsuitedforapplicationsrequiringmultiplesensorinformationanddriveactuatorswithcomplexandaccuratetimepulses.AHighEndTimerTransferUnit(HET-TU)canperformDMAtypetransactionstotransferN2HETdatatoorfrommainmemory.AMemoryProtectionUnit(MPU)isbuiltintotheHET-TU.Thedevicehastwo12-bit-resolutionMibADCswith24totalchannelsand64wordsofparityprotectedbufferRAMeach.TheMibADCchannelscanbeconvertedindividuallyorcanbegroupedbysoftwareforsequentialconversionsequences.SixteenchannelsaresharedbetweenthetwoMibADCs.Therearethreeseparategroupings.Eachsequencecanbeconvertedoncewhentriggeredorconfiguredforcontinuousconversionmode.Thedevicehasmultiplecommunicationinterfaces:threeMibSPIs,uptotwoSPIs,oneLIN,oneSCI,threeDCANs,oneI2C.TheSPIprovidesaconvenientmethodofserialinteractionforhigh-speedcommunicationsbetweensimilarshift-registertypedevices.TheLINsupportstheLocalInterconnectstandard2.0andcanbeusedasaUARTinfull-duplexmodeusingthestandardNon-Return-to-Zero(NRZ)format.TheDCANsupportstheCAN2.0Bprotocolstandardandusesaserial,multimastercommunicationprotocolthatefficientlysupportsdistributedreal-timecontrolwithrobustcommunicationratesofupto1megabitpersecond(Mbps).TheDCANisidealforapplicationsoperatinginnoisyandharshenvironments(e.g.,automotiveandindustrialfields)thatrequirereliableserialcommunicationormultiplexedwiring.TheI2Cmoduleisamulti-mastercommunicationmoduleprovidinganinterfacebetweenthemicrocontrollerandanI2CcompatibledeviceviatheI2Cserialbus.TheI2Csupportsboth100Kbpsand400Kbpsspeeds.Thefrequency-modulatedphase-lockedloop(FMPLL)clockmoduleisusedtomultiplytheexternalfrequencyreferencetoahigherfrequencyforinternaluse.TheFMPLLprovidesoneofthesevenpossibleclocksourceinputstotheglobalclockmodule(GCM).TheGCMmodulemanagesthemappingbetweentheavailableclocksourcesandthedeviceclockdomains.Thedevicealsohasanexternalclockprescaler(ECP)modulethatwhenenabled,outputsacontinuousexternalclockontheECLKpin/ball.TheECLKfrequencyisauser-programmableratiooftheperipheralinterfaceclock(VCLK)frequency.Thislowfrequencyoutputcanbemonitoredexternallyasanindicatorofthedeviceoperatingfrequency.TheDirectMemoryAccessController(DMA)has16channels,32controlpacketsandparityprotectiononitsmemory.AMemoryProtectionUnit(MPU)isbuiltintotheDMAtoprotectmemoryagainsterroneoustransfers.TheErrorSignalingModule(ESM)monitorsalldeviceerrorsanddetermineswhetheraninterruptorexternalErrorpin/ballistriggeredwhenafaultisdetected.ThenERRORcanbemonitoredexternallyasanindicatorofafaultconditioninthemicrocontroller.TheExternalMemoryInterface(EMIF)providesamemoryextensiontoasynchronousandsynchronousmemoriesorotherslavedevices.Severalinterfacesareimplementedtoenhancethedebuggingcapabilitiesofapplicationcode.InadditiontothebuiltinARMCortex™-R4FCoreSight™debugfeatures.AnExternalTraceMacrocell(ETM)providesinstructionanddatatraceofprogramexecution.Forinstrumentationpurposes,aRAMTracePortModule(RTP)isimplementedtosupporthigh-speedtracingofRAMandperipheralaccessesbytheCPUoranyothermaster.ADataModificationModule(DMM)givestheabilitytowriteexternaldataintothedevicememory.BoththeRTPandDMMhavenooronlyminimumimpactontheprogramexecutiontimeoftheapplicationcode.AParameterOverlayModule(PO