ATMEGA8L-8AU

Features•High-performance,Low-powerAVR®8-bitMicrocontroller•AdvancedRISCArchitecture–130PowerfulInstructions–MostSingle-clockCycleExecution–32x8GeneralPurposeWorkingRegisters–FullyStaticOperation–Upto16MIPSThroughputat16MHz–On-chip2-cycleMultiplier•NonvolatileProgramandDataMemories–8KBytesofIn-SystemSelf-ProgrammableFlashEndurance:10,000Write/EraseCycles–OptionalBootCodeSectionwithIndependentLockBitsIn-SystemProgrammingbyOn-chipBootProgramTrueRead-While-WriteOperation–512BytesEEPROMEndurance:100,000Write/EraseCycles–1KByteInternalSRAM–ProgrammingLockforSoftwareSecurity•PeripheralFeatures–Two8-bitTimer/CounterswithSeparatePrescaler,oneCompareMode–One16-bitTimer/CounterwithSeparatePrescaler,CompareMode,andCaptureMode–RealTimeCounterwithSeparateOscillator–ThreePWMChannels–8-channelADCinTQFPandQFN/MLFpackageEightChannels10-bitAccuracy–6-channelADCinPDIPpackageEightChannels10-bitAccuracy–Byte-orientedTwo-wireSerialInterface–ProgrammableSerialUSART–Master/SlaveSPISerialInterface–ProgrammableWatchdogTimerwithSeparateOn-chipOscillator–On-chipAnalogComparator•SpecialMicrocontrollerFeatures–Power-onResetandProgrammableBrown-outDetection–InternalCalibratedRCOscillator–ExternalandInternalInterruptSources–FiveSleepModes:Idle,ADCNoiseReduction,Power-save,Power-down,andStandby•I/OandPackages–23ProgrammableI/OLines–28-leadPDIP,32-leadTQFP,and32-padQFN/MLF•OperatingVoltages–2.7-5.5V(ATmega8L)–4.5-5.5V(ATmega8)•SpeedGrades–0-8MHz(ATmega8L)–0-16MHz(ATmega8)•PowerConsumptionat4Mhz,3V,25èC–Active:3.6mA–IdleMode:1.0mA–Power-downMode:0.5µA8-bitwi[e-mail]8ATmega8L2486QS–AVR–10/06PinConfigurations(RESET)PC6(RXD)PD0(TXD)PD1(INT0)PD2(INT1)PD3(XCK/T0)PD4VCCGND(XTAL1/TOSC1)PB6(XTAL2/TOSC2)PB7(T1)PD5(AIN0)PD6(AIN1)PD7(ICP1)PB01234567891011121314PDIP2827262524232221201918171615PC5(ADC5/SCL)PC4(ADC4/SDA)PC3(ADC3)PC2(ADC2)PC1(ADC1)PC0(ADC0)GNDAREFAVCCPB5(SCK)PB4(MISO)PB3(MOSI/OC2)PB2(SS/OC1B)PB1(OC1A)2ATmega8(L)(INT1)PD3(XCK/T0)PD4GNDVCCGNDVCC(XTAL1/TOSC1)PB6(XTAL2/TOSC2)PB7(INT1)PD3(XCK/T0)PD4GNDVCCGNDVCC(XTAL1/TOSC1)PB6(XTAL2/TOSC2)PB71234567812345678TQFPTopViewMLFTopView24232221201918172423222120191817PC1(ADC1)PC0(ADC0)ADC7GNDAREFADC6AVCCPB5(SCK)PC1(ADC1)PC0(ADC0)ADC7GNDAREFADC6AVCCPB5(SCK)NOTE:ThelargecenterpadunderneaththeMLFpackagesismadeofmetalandinternallyconnectedtoGND.ItshouldbesolderedorgluedtothePCBtoensuregoodmechanicalstability.Ifthecenterpadisleftunconneted,thepackagemightloosenfromthePCB.2486QS–AVR–10/063231302928272625910111213141516(T1)PD5(AIN0)PD6(AIN1)PD7(ICP1)PB0(OC1A)PB1(SS/OC1B)PB2(MOSI/OC2)PB3(MISO)PB4PD2(INT0)PD1(TXD)PD0(RXD)PC6(RESET)PC5(ADC5/SCL)PC4(ADC4/SDA)PC3(ADC3)PC2(ADC2)3231302928272625910111213141516(T1)PD5(AIN0)PD6(AIN1)PD7(ICP1)PB0(OC1A)PB1(SS/OC1B)PB2(MOSI/OC2)PB3(MISO)PB4PD2(INT0)PD1(TXD)PD0(RXD)PC6(RESET)PC5(ADC5/SCL)PC4(ADC4/SDA)PC3(ADC3)PC2(ADC2)OverviewBlockDiagramATmega8(L)TheATmega8isalow-powerCMOS8-bitmicrocontrollerbasedontheAVRRISCarchitecture.Byexecutingpowerfulinstructionsinasingleclockcycle,theATmega8achievesthroughputsapproaching1MIPSperMHz,allowingthesystemdesignertooptimizepowerconsumptionversusprocessingspeed.Figure1.BlockDiagramXTAL1RESETPC0-PC6PB0-PB7VCCXTAL2PORTCDRIVERS/BUFFERSPORTBDRIVERS/BUFFERSGNDAGNDAREFPORTCDIGITALINTERFACEMUX&ADCADCINTERFACEPORTBDIGITALINTERFACETWITIMERS/PROGRAMSTACKCOUNTERPOINTERPROGRAMCOUNTERSINTERNALOSCILLATORFLASHINSTRUCTIONREGISTERINSTRUCTIONDECODERCONTROLLINESAVRCPUPROGRAMMINGLOGIC+-SRAMGENERALPURPOSEREGISTERSXYZALUSTATUSREGISTERSPICOMP.INTERFACEOSCILLATORWATCHDOGTIMERMCUCTRL.&TIMINGINTERRUPTUNITEEPROMUSARTOSCILLATOR2486QS–AVR–10/06PORTDDIGITALINTERFACEPORTDDRIVERS/BUFFERSPD0-PD73DisclaimerTheAVRcorecombinesarichinstructionsetwith32generalpurposeworkingregisters.Allthe32registersaredirectlyconnectedtotheArithmeticLogicUnit(ALU),allowingtwoindependentregisterstobeaccessedinonesingleinstructionexecutedinoneclockcycle.TheresultingarchitectureismorecodeefficientwhileachievingthroughputsuptotentimesfasterthanconventionalCISCmicrocontrollers.TheATmega8providesthefollowingfeatures:8KbytesofIn-SystemProgrammableFlashwithRead-While-Writecapabilities,512bytesofEEPROM,1KbyteofSRAM,23generalpurposeI/Olines,32generalpurposeworkingregisters,threeflexibleTimer/Counterswithcomparemodes,internalandexternalinterrupts,aserialprogram-mableUSART,abyteorientedTwo-wireSerialInterface,a6-channelADC(eightchannelsinTQFPandQFN/MLFpackages)with10-bitaccuracy,aprogrammableWatchdogTimerwithInternalOscillator,anSPIserialport,andfivesoftwareselectablepowersavingmodes.TheIdlemodestopstheCPUwhileallowingtheSRAM,Timer/Counters,SPIport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheregistercontentsbutfreezestheOscillator,disablingallotherchipfunctionsuntilthenextInterruptorHardwareReset.InPower-savemode,theasynchronoustimercontinuestorun,allowingtheusertomaintainatimerbasewhiletherestofthedeviceissleeping.TheADCNoiseReductionmodestopstheCPUandallI/Omodulesexceptasynchronoustimera