SST37VF010-70-3C-NHE中文资料

©2006SiliconStorageTechnology,Inc.S71151-07-0008/061TheSSTlogoandSuperFlashareregisteredtrademarksofSiliconStorageTechnology,Inc.MTPisatrademarkofSiliconStorageTechnology,Inc.Thesespecificationsaresubjecttochangewithoutnotice.DataSheet512Kbit/1Mbit/2Mbit/4Mbit(x8)Many-TimeProgrammableFlashSST37VF512/SST37VF010/SST37VF020/SST37VF040FEATURES:•Organizedas64Kx8/128Kx8/256Kx8/512Kx8�2.7-3.6VReadOperation�SuperiorReliability–Endurance:Atleast1000Cycles–Greaterthan100yearsDataRetention�LowPowerConsumption:–ActiveCurrent:10mA(typical)–StandbyCurrent:2µA(typical)�FastReadAccessTime:–70ns�LatchedAddressandData�FastByte-ProgramOperation:–Byte-ProgramTime:15µs(typical)–ChipProgramTime:1seconds(typical)forSST37VF5122seconds(typical)forSST37VF0104seconds(typical)forSST37VF0208seconds(typical)forSST37VF040�ElectricalEraseUsingProgrammer–DoesnotrequireUVsource–Chip-EraseTime:100ms(typical)�CMOSI/OCompatibility�JEDECStandardByte-wideFlashEEPROMPinouts�PackagesAvailable–32-leadPLCC–32-leadTSOP(8mmx14mm)–32-pinPDIP–Non-Pb(lead-free)packagesavailablePRODUCTDESCRIPTIONTheSST37VF512/010/020/040devicesare64Kx8/128Kx8/256Kx8/512Kx8CMOS,Many-TimeProgrammable(MTP),lowcostflash,manufacturedwithSST’sproprietary,highperformanceCMOSSuperFlashtechnology.Thesplit-gatecelldesignandthick-oxidetunnelinginjectorattainbetterreliabilityandmanufacturabilitycomparedwithalternateapproaches.TheSST37VF512/010/020/040canbeelectricallyerasedandprogrammedatleast1000timesusinganexternalprogrammer,e.g.,tochangethecontentsofdevicesininventory.TheSST37VF512/010/020/040havetobeerasedpriortoprogramming.ThesedevicesconformtoJEDECstandardpinoutsforbyte-wideflashmemories.FeaturinghighperformanceByte-Program,theSST37VF512/010/020/040provideatypicalByte-Pro-gramtimeof15µs.Designed,manufactured,andtestedforawidespectrumofapplications,thesedevicesareofferedwithanenduranceofatleast1000cycles.Dataretentionisratedatgreaterthan100years.TheSST37VF512/010/020/040aresuitedforapplicationsthatrequireinfrequentwritesandlowpowernonvolatilestorage.Thesedeviceswillimproveflexibility,efficiency,andperformancewhilematchingthelowcostinnonvolatileapplicationsthatcurrentlyuseUV-EPROMs,OTPs,andmaskROMs.Tomeetsurfacemountandconventionalthroughholerequirements,theSST37VF512/010/020/040areofferedin32-leadPLCC,32-leadTSOP,and32-pinPDIPpackages.SeeFigures2,3,and4forpinassignments.DeviceOperationTheSST37VF512/010/020/040devicesarenonvolatilememorysolutionsthatcanbeusedinsteadofstandardflashdevicesifin-systemprogrammabilityisnotrequired.Itisfunctionally(Read)andpincompatiblewithindustrystandardflashproducts.ThedevicesupportselectricalEraseoperationviaanexternalprogrammer.ReadTheReadoperationoftheSST37VF512/010/020/040iscontrolledbyCE#andOE#.BothCE#andOE#havetobelowforthesystemtoobtaindatafromtheoutputs.Oncetheaddressisstable,theaddressaccesstimeisequaltothedelayfromCE#tooutput(TCE).DataisavailableattheoutputafteradelayofTOEfromthefallingedgeofOE#,assumingtheCE#pinhasbeenlowandtheaddresseshavebeenstableforatleastTCE-TOE.WhentheCE#pinishigh,thechipisdeselectedandastandbycurrentofonly2µA(typical)isconsumed.OE#istheoutputcontrolandisusedtogatedatafromtheoutputpins.ThedatabusisinhighimpedancestatewheneitherCE#orOE#isVIH.RefertoFigure5forthetimingdiagram.SST37VF512/010/020/0402.7V-Read512Kb/1Mb/2Mb/4Mb(x8)MTPflashmemories2DataSheet512Kbit/1Mbit/2Mbit/4MbitMany-TimeProgrammableFlashSST37VF512/SST37VF010/SST37VF020/SST37VF040©2006SiliconStorageTechnology,Inc.S71151-07-0008/06Byte-ProgramOperationTheSST37VF512/010/020/040areprogrammedbyusinganexternalprogrammer.Theprogrammingmodeisacti-vatedbyasserting11.4-12VonOE#pinandVILonCE#pin.Thedeviceisprogrammedusingasinglepulse(WE#pinlow)of15µsperbyte.UsingtheMTPprogrammingalgorithm,theByte-Programprocesscontinuesbyte-by-byteuntiltheentirechiphasbeenprogrammed.RefertoFigure11fortheflowchartandFigure7forthetimingdia-gram.Chip-EraseOperationTheonlywaytochangeadatafroma“0”to“1”isbyelectricalerasethatchangeseverybitinthedeviceto“1”.TheSST37VF512/010/020/040useanelectricalChip-Eraseoperation.Theentirechipcanbeerasedin100ms(WE#pinlow).Inordertoactivateerasemode,the11.4-12VisappliedtoOE#andA9pinswhileCE#islow.Allotheraddressanddatapinsare“don’tcare”.ThefallingedgeofWE#willstarttheChip-Eraseoperation.Oncethechiphasbeenerased,allbytesmustbeverifiedforFFH.RefertoFigure10fortheflowchartandFigure6forthetimingdiagram.ProductIdentificationModeTheProductIdentificationmodeidentifiesthedevicesasSST37VF512,SST37VF010,SST37VF020,andSST37VF040andmanufacturerasSST.Thismodemaybeaccessedbythehardwaremethod.Toactivatethismode,theprogrammingequipmentmustforceVH(11.4-12V)onaddressA9.TwoidentifierbytesmaythenbesequencedfromthedeviceoutputsbytogglingaddresslineA0.Fordetails,seeTable3forhardwareoperation.DesignConsiderationsTheSST37VF512/010/020/040shouldhavea0.1µFceramichighfrequency,lowinductancecapacitorcon-nectedbetweenVDDandGND.Thiscapacitorshouldbeplacedasclosetothepackageterminalsaspossible.OE#andA9mustremainstableatVHfortheentiredura-tionofanEraseoperation.OE#mustremainstableat