THC63LVD823中文资料

THC63LVD823_Rev2.0Copyright2000-2003THineElectronics,Inc.Allrightsreserved1THineElectronics,Inc.THC63LVD823Single(135MHz)/Dual(170MHz)LinkLVDSTransmitterforSXGA/SXGA+/UXGAGeneralDescriptionTheTHC63LVD823transmitterisdesignedtosupportSingleLinktransmissionbetweenHostandFlatPanelDisplayuptoSXGA+resolutionsandDualLinktrans-missionbetweenHostandFlatPanelDisplayuptoUXGAresolutions.TheTHC63LVD823converts48bitsofCMOS/TTLdataintoLVDS(LowVoltageDifferentialSignaling)datastream.Thetransmittercanbeprogrammedforris-ingedgeorfallingedgeclocksthroughadedicatedpin.InSingleLink,thetransmitclockfrequencyof135MHz,48bitsofRGBdataaretransmittedataneffectiverateof945MbpsperLVDSchannel.Usinga135MHzclock,thedatathroughputis472Mbytespersecond.InDualLink,thetransmitclockfrequencyof85MHz,48bitsofRGBdataaretransmittedataneffectiverateof595MbpsperLVDSchannel.Usinga85MHzclock,thedatathroughputis595Mbytespersecond.Features•Widedotclockrange:25-135MHzsuitedforVGA,SVGA,XGA,SXGA,SXGA+andUXGA•PLLrequiresNoexternalcomponents•SupportsDualLink,Dual-in(TTL)/Dual-out(LVDS)pixelupto170MHzdotclockforUXGA•SupportsSingleLink,Dual-in(TTL)/Single-out(LVDS)pixelupto135MHzdotclockforSXGA+•SupportsSingleLink,Single-in(TTL)/Single-out(LVDS)pixelupto85MHzdotclockforXGA•Clockedgeselectable•SupportsReducedswingLVDSforLowEMI•Powerdownmode•Lowpowersingle3.3VCMOSdesign•100pinTQFP•THC63LVDM83RcompatibleBlockDiagramPARALLELTOSERIALPLLTA1+/-TB1+/-TC1+/-TD1+/-TCLK1+/-R/F/PDWN(25to135MHz)1stLink8RED1GREEN1BLUE1HSYNCVSYNCDERED2GREEN2BLUE2TRANSMITTERCLOCKIN(25to85MHz)1stDATA2ndDATACMOS/TTLINPUTPARALLELTOSERIALTA2+/-TB2+/-TC2+/-TD2+/-TCLK2+/-MUX88888888(25to85MHz)2ndLinkLVDSOUTPUTCopyright2000-2003THineElectronics,Inc.Allrightsreserved2THineElectronics,Inc.THC63LVD823_Rev2.0PinOutB15B16B17R20R21R22R23R24R25R26R27VCCGNDG20G21G22G23G24G25G26G27B20B21B22B23767778798081828384858687888990919293949596979899100LVDSGNDTA1-TA1+TB1-TB1+LVDSVCCTC1-TC1+TCLK1-TCLK1+TD1-TD1+LVDSGNDTA2-TA2+TB2-TB2+LVDSVCCTC2-TC2+TCLK2-TCLK2+TD2-TD2+LVDSGND50494847464544434241403938373635343332313029282726B24B25VCCGNDB26B27HSYNCVSYNCDECLKINR/FRSTEST1TEST2MODE1MODE0OE6/8/PDWNTEST3TEST4TEST5PLLGNDPLLVCCPLLGND12345678910111213141516171819202122232425B14B13B12GNDVCCB11B10G17G16G15G14G13G12G11G10R17R16R15R14GNDVCCR13R12R11R1075747372717069686766656463626160595857565554535251Copyright2000-2003THineElectronics,Inc.Allrightsreserved3THineElectronics,Inc.THC63LVD823_Rev2.0PinDescriptionPinNamePin#TypeDescriptionTA1+,TA1-48,49LVDSOUTThe1stLink.The1stpixeloutputdatawhenDualLink.TB1+,TB1-46,47LVDSOUTTC1+,TC1-43,44LVDSOUTTD1+,TD1-39,40LVDSOUTTCLK1+,TCLK1-41,42LVDSOUTLVDSClockOutfor1stLink.TA2+,TA2-36,37LVDSOUTThe2ndLink.ThesepinsaredisabledwhenSingleLink.TB2+,TB2-34,35LVDSOUTTC2+,TC2-31,32LVDSOUTTD2+,TD2-27,28LVDSOUTTCLK2+,TCLK2-29,30LVDSOUTLVDSClockOutfor2ndLink.R17~R1060,59,58,57,54,53,52,51INThe1stPixelDataInputs.G17~G1068,67,66,65,64,63,62,61INB17~B1078,77,76,75,74,73,70,69INR27~R2086,85,84,83,82,81,80,79INThe2ndPixelDataInputs.G27~G2096,95,94,93,92,91,90,89INB27~B206,5,2,1,100,99,98,97INDE9INDataEnableInput.VSYNC8INVsyncInput.HSYNC7INHsyncInput.CLKIN10INClockInput.TEST1,TEST513,22OUTTestPins.TEST3,TEST420,21INTestPins,mustbeLfornormaloperation.TEST214INTestPins,mustbeHfornormaloperation./PDWN19INH:Normaloperation,L:Powerdown(alloutputsareHi-Z)6/818IN6bit/8bitcolorselect.H:6bit(TDx+/-areGND),L:8bit.OE17INOutputenable.H:Outputenable,L:Outputdisable(alloutputsareHi-Z)MODE1,MODE015,16INRS12INLVDSswingrangeselect.H:Normalrange,L:Reducedrange.PixelDataMode.MODE1MODE0ModeLLDualLink(Dual-in/Dual-out)LHSingleLink(Dual-in/Single-out)HHSingleLink(Single-in/Single-out)Copyright2000-2003THineElectronics,Inc.Allrightsreserved4THineElectronics,Inc.THC63LVD823_Rev2.0AbsoluteMaximumRatings1ElectricalCharacteristicsCMOS/TTLDCSpecificationsVCC=3.0V~3.6V,Ta=-10~+70R/F11INInputClockTriggeringEdgeSelect.H:Risingedge,L:FallingedgeVCC3,55,71,87PowerPowerSupplyPinsforTTLinputs,outputanddigitalcircuitry.GND4,56,72,88GroundGroundPinsforTTLinputs,outputsanddigitalcircuitry.LVDSVCC33,45PowerPowerSupplyPinsforLVDSOutputs.LVDSGND26,38,50GroundGroundPinsforLVDSOutputs.PLLVCC24PowerPowerSupplyforPLLcircuitry.PLLGND23,25GroundGroundPinforPLLcircuitry.SupplyVoltage(VCC)-0.3V~+4.0VCMOS/TTLInputVoltage-0.3V~(VCC+0.3V)CMOS/TTLOutputVoltage-0.3V~(VCC+0.3V)LVDSDriverOutputVoltage-0.3V~(VCC+0.3V)OutputCurrent-30mA~30mAJunctionTemperature+125StorageTemperatureRange-55~+125LeadTemperature(Soldering,4sec)+260MaximumPowerDissipation@+251.0W1.“AbsoluteMaximumRatings”arethosevaluedbeyondwhichthesafetyofthedevicecannotbeguaranteed.Theyarenotmeanttoimplythatthedeviceshouldbeoperatedattheselimits.Thetablesof“ElectricalCharacteristics”specifyconditionsfordeviceoperation.SymbolParameterConditionsMin.Typ.Max.UnitsVIHHighLevelInputVoltage2.0VCCVVILLowLevelInputVoltageGND0.8VIINCInputCurrentµAPinNamePin#TypeDescription°C°C°C°C°C°C°C0VVINVCC≤≤10±Copyright2000-2003THineElectronics,Inc.Allrightsreserved5THineElectronics,Inc.THC63LVD823_Rev2.0LVDSTransmitterDCSpecifi