CMOS超大规模集成电路设计课件

Lecture1:Circuits&LayoutCMOSVLSIDesign4thEd.1:Circuits&Layout2OutlineABriefHistoryCMOSGateDesignPassTransistorsCMOSLatches&Flip-FlopsStandardCellLayoutsStickDiagramsCMOSVLSIDesign4thEd.1:Circuits&Layout3ABriefHistory1958:Firstintegratedcircuit–Flip-flopusingtwotransistors–BuiltbyJackKilbyatTexasInstruments2010–IntelCorei7mprocessor•2.3billiontransistors–64GbFlashmemory•16billiontransistorsCourtesyTexasInstruments[Trinh09]©2009IEEE.CMOSVLSIDesign4thEd.1:Circuits&Layout4GrowthRate53%compoundannualgrowthrateover50years–NoothertechnologyhasgrownsofastsolongDrivenbyminiaturizationoftransistors–Smallerischeaper,faster,lowerinpower!–Revolutionaryeffectsonsociety[Moore65]ElectronicsMagazineCMOSVLSIDesign4thEd.1:Circuits&Layout5AnnualSales1019transistorsmanufacturedin2008–1billionforeveryhumanontheplanetCMOSVLSIDesign4thEd.1:Circuits&Layout6InventionoftheTransistorVacuumtubesruledinfirsthalfof20thcenturyLarge,expensive,power-hungry,unreliable1947:firstpointcontacttransistor–JohnBardeenandWalterBrattainatBellLabs–SeeCrystalFirebyRiordan,HoddesonAT&TArchives.Reprintedwithpermission.CMOSVLSIDesign4thEd.1:Circuits&Layout7TransistorTypesBipolartransistors–npnorpnpsiliconstructure–Smallcurrentintoverythinbaselayercontrolslargecurrentsbetweenemitterandcollector–BasecurrentslimitintegrationdensityMetalOxideSemiconductorFieldEffectTransistors–nMOSandpMOSMOSFETS–Voltageappliedtoinsulatedgatecontrolscurrentbetweensourceanddrain–LowpowerallowsveryhighintegrationCMOSVLSIDesign4thEd.1:Circuits&Layout81970’sprocessesusuallyhadonlynMOStransistors–Inexpensive,butconsumepowerwhileidle1980s-present:CMOSprocessesforlowidlepowerMOSIntegratedCircuitsIntel1101256-bitSRAMIntel40044-bitmProc[Vadasz69]©1969IEEE.IntelMuseum.Reprintedwithpermission.CMOSVLSIDesign4thEd.1:Circuits&Layout9Moore’sLaw:Then1965:GordonMooreplottedtransistoroneachchip–Fitstraightlineonsemilogscale–Transistorcountshavedoubledevery26monthsIntegrationLevelsSSI:10gatesMSI:1000gatesLSI:10,000gatesVLSI:10kgates[Moore65]ElectronicsMagazineCMOSVLSIDesign4thEd.1:Circuits&Layout10AndNow…CMOSVLSIDesign4thEd.1:Circuits&Layout11FeatureSizeMinimumfeaturesizeshrinking30%every2-3yearsCMOSVLSIDesign4thEd.1:Circuits&Layout12CorollariesManyotherfactorsgrowexponentially–Ex:clockfrequency,processorperformanceCMOSVLSIDesign4thEd.1:Circuits&Layout13CMOSGateDesignActivity:–Sketcha4-inputCMOSNORgateABCDYCMOSVLSIDesign4thEd.1:Circuits&Layout14ComplementaryCMOSComplementaryCMOSlogicgates–nMOSpull-downnetwork–pMOSpull-upnetwork–a.k.a.staticCMOSpMOSpull-upnetworkoutputinputsnMOSpull-downnetworkPull-upOFFPull-upONPull-downOFFZ(float)1Pull-downON0X(crowbar)CMOSVLSIDesign4thEd.1:Circuits&Layout15SeriesandParallelnMOS:1=ONpMOS:0=ONSeries:bothmustbeONParallel:eithercanbeON(a)ababg1g200ab01ab10ab11OFFOFFOFFON(b)ababg1g200ab01ab10ab11ONOFFOFFOFF(c)ababg1g200OFFONONON(d)ONONONOFFab0ab1ab1101ab00ab0ab1ab1101abg1g2CMOSVLSIDesign4thEd.1:Circuits&Layout16ConductionComplementComplementaryCMOSgatesalwaysproduce0or1Ex:NANDgate–SeriesnMOS:Y=0whenbothinputsare1–ThusY=1wheneitherinputis0–RequiresparallelpMOSRuleofConductionComplements–Pull-upnetworkiscomplementofpull-down–Parallel-series,series-parallelABYCMOSVLSIDesign4thEd.1:Circuits&Layout17CompoundGatesCompoundgatescandoanyinvertingfunctionEx:(AND-AND-OR-INVERT,AOI22)YABCDABCDABCDABCDABCDBDYACACABCDBDY(a)(c)(e)(b)(d)(f)CMOSVLSIDesign4thEd.1:Circuits&Layout18Example:O3AIYABCDABYCDDCBACMOSVLSIDesign4thEd.1:Circuits&Layout19SignalStrengthStrengthofsignal–HowcloseitapproximatesidealvoltagesourceVDDandGNDrailsarestrongest1and0nMOSpassstrong0–Butdegradedorweak1pMOSpassstrong1–Butdegradedorweak0ThusnMOSarebestforpull-downnetworkCMOSVLSIDesign4thEd.1:Circuits&Layout20PassTransistorsTransistorscanbeusedasswitchesg=0sdg=1sd0strong0InputOutput1degraded1g=0sdg=1sd0degraded0InputOutputstrong1g=1g=1g=0g=01gsdgsdCMOSVLSIDesign4thEd.1:Circuits&Layout21TransmissionGatesPasstransistorsproducedegradedoutputsTransmissiongatespassboth0and1wellg=0,gb=1abg=1,gb=0ab0strong0InputOutput1strong1ggbababggbabggbabggbg=1,gb=0g=1,gb=0CMOSVLSIDesign4thEd.1:Circuits&Layout22TristatesTristatebufferproducesZwhennotenabledENAY00Z01Z100111AYENAYENENCMOSVLSIDesign4thEd.1:Circuits&Layout23NonrestoringTristateTransmissiongateactsastristatebuffer–Onlytwotransistors–Butnonrestoring•NoiseonAispassedontoYAYENENCMOSVLSIDesign4thEd.1:Circuits&Layout24TristateInverterTristateinverterproducesrestoredoutput–Violatesconductioncomplementrule–BecausewewantaZoutputAYENAYEN=0Y='Z'YEN=1Y=AAENCMOSVLSIDesign4thEd.1:Circuits&Layout25Multiplexers2:1multiplexerchoosesbetweentwoinputsSD1D0Y0X000X1110X011X101SD0D1YCMOSVLSIDesign4thEd.1:Circuits&Layout26Gate-LevelMuxDesignHowmanytransistorsareneeded?2010(toomanytransistors)YSDSD44D1D0SY4222Y2D1D0SCMOSVLSIDesign4thEd.1:Circuits&Layout27TransmissionGateMuxNonrestoringmuxusestwotransmissiongates–Only4transistorsSSD0D1YSCMOSVLSIDesign4thEd.1:Circuits&Layout28InvertingMuxInvertingmultiplexer–UsecompoundAOI22–Orpairo