计算机组成原理与体系结构_05_Internal Memory

WilliamStallingsComputerOrganizationandArchitecture7thEditionChapter5InternalMemorySemiconductorMemoryTypesSemiconductorMemory•RAM—Misnamedasallsemiconductormemoryisrandomaccess—Read/Write—Volatile—Temporarystorage—StaticordynamicMemoryCellOperationDynamicRAM•Bitsstoredaschargeincapacitors•Chargesleak•Needrefreshingevenwhenpowered•Simplerconstruction•Smallerperbit•Lessexpensive•Needrefreshcircuits•Slower•Mainmemory•Essentiallyanalogue—LevelofchargedeterminesvalueDynamicRAMStructureDRAMOperation•Addresslineactivewhenbitreadorwritten—Transistorswitchclosed(currentflows)•Write—Voltagetobitline–Highfor1lowfor0—Thensignaladdressline–Transferschargetocapacitor•Read—Addresslineselected–transistorturnson—Chargefromcapacitorfedviabitlinetosenseamplifier–Compareswithreferencevaluetodetermine0or1—CapacitorchargemustberestoredStaticRAM•Bitsstoredason/offswitches•Nochargestoleak•Norefreshingneededwhenpowered•Morecomplexconstruction•Largerperbit•Moreexpensive•Doesnotneedrefreshcircuits•Faster•Cache•Digital—Usesflip-flopsStatingRAMStructureStaticRAMOperation•Transistorarrangementgivesstablelogicstate•State1—C1high,C2low—T1T4off,T2T3on•State0—C2high,C1low—T2T3off,T1T4on•AddresslinetransistorsT5T6isswitch•Write–applyvaluetoB&complimenttoB•Read–valueisonlineBSRAMvDRAM•Bothvolatile—Powerneededtopreservedata•Dynamiccell—Simplertobuild,smaller—Moredense—Lessexpensive—Needsrefresh—Largermemoryunits•Static—Faster—CacheReadOnlyMemory(ROM)•Permanentstorage—Nonvolatile•Microprogramming(seelater)•Librarysubroutines•Systemsprograms(BIOS)•FunctiontablesTypesofROM•Writtenduringmanufacture—Veryexpensiveforsmallruns•Programmable(once)—PROM—Needsspecialequipmenttoprogram•Read“mostly”—ErasableProgrammable(EPROM)–ErasedbyUV—ElectricallyErasable(EEPROM)–Takesmuchlongertowritethanread—Flashmemory–Erasewholememoryelectrically地址译码驱动系统•（1）地址译码器的功能：把CPU给定的地址码翻译成能驱动指定存储单元的控制信息。(n----2ⁿ)•（2）简单译码器电路•（3）“驱动”的含义。•（4）地址译码系统的设计——一维和二维地址译码方案及选择•例：1KX4位RAM的地址译码方案。•A0字线w00•字线W01••A1字线W10•字线W11••A0A0A1A1&&&&地址译码系统的设计例子：1KX4位RAM•一维地址译码方案：存储体阵列的每一个存储单元由一条字线驱动。也叫单译码结构。例中用此方案共需字线条数为：1024条•二维地址译码方案：从CPU来的地址线分成两部分，分别进入X（横向）地址译码器和Y（纵向）地址译码器，由二者同时有效的字线交叉选中一个存储单元。•例中将1KX4RAM的10条地址线中6条（A0~A5）用在横向，4条（A6~A9）用在纵向，则共产生字线条数为：64+16=80条•1KX4位RAM二维地址译码的图示：X地址译码器I/OI/OI/OI/OY地址译码器位扩展1使用8KX1的RAM存储芯片组成8KX4的存储器。中央处理器地址总线8KX138KX148KX128KX11数据总线D3D1D0D2字扩展2用8KX4的芯片组成32KX4的存储器。A14A13A0A12WED0—D3CPU2：4译码器CE8KX4WECE8KX4WECE8KX4WECE8KX4WE（一）扩展方法的实例：现有2114即1KX4RAM芯片，要构成8KX16位主存，应该用多少片2114？画出扩展、连接图。A0……A9R/W2114(1#)CSD3D2D1D0A0……A9R/W2114(4#)CSD3D2D1D0•首先计算用多少片2114：（8KX16）/（1KX4）=32片•然后进行位扩展：把1KX4扩成1KX16，用16/4=4片•A9CS•A0•D15•D12例题两个：1，2见中文课件4。P33-40要求掌握。Organisationindetail•A16Mbitchipcanbeorganisedas1Mof16bitwords•Abitperchipsystemhas16lotsof1Mbitchipwithbit1ofeachwordinchip1andsoon•A16Mbitchipcanbeorganisedasa2048x2048x4bitarray—Reducesnumberofaddresspins–Multiplexrowaddressandcolumnaddress–11pinstoaddress(211=2048)–Addingonemorepindoublesrangeofvaluessox4capacityRefreshing•Refreshcircuitincludedonchip•Disablechip•Countthroughrows•Read&Writeback•Takestime•SlowsdownapparentperformanceTypical16MbDRAM(4Mx4)Packaging256kByteModuleOrganisation1MByteModuleOrganisationErrorCorrection•HardFailure—Permanentdefect•SoftError—Random,non-destructive—Nopermanentdamagetomemory•DetectedusingHammingerrorcorrectingcodeErrorCorrectingCodeFunctionAdvancedDRAMOrganization•BasicDRAMsamesincefirstRAMchips•EnhancedDRAM—ContainssmallSRAMaswell—SRAMholdslastlineread(c.f.Cache!)•CacheDRAM—LargerSRAMcomponent—UseascacheorserialbufferSynchronousDRAM(SDRAM)•Accessissynchronizedwithanexternalclock•AddressispresentedtoRAM•RAMfindsdata(CPUwaitsinconventionalDRAM)•SinceSDRAMmovesdataintimewithsystemclock,CPUknowswhendatawillbeready•CPUdoesnothavetowait,itcandosomethingelse•BurstmodeallowsSDRAMtosetupstreamofdataandfireitoutinblock•DDR-SDRAMsendsdatatwiceperclockcycle(leading&trailingedge)SDRAMSDRAMReadTimingRAMBUS•AdoptedbyIntelforPentium&Itanium•MaincompetitortoSDRAM•Verticalpackage–allpinsononeside•Dataexchangeover28wirescmlong•Busaddressesupto320RDRAMchipsat1.6Gbps•Asynchronousblockprotocol—480nsaccesstime—Then1.6GbpsRAMBUSDiagramDDRSDRAM•SDRAMcanonlysenddataonceperclock•Double-data-rateSDRAMcansenddatatwiceperclockcycle—RisingedgeandfallingedgeCacheDRAM•Mitsubishi•IntegratessmallSRAMcache(16kb)ontogenericDRAMchip•Usedastruecache—64-bitlines—Effectiveforordinaryrandomaccess•Tosupportserialaccessofblockofdata—E.g.refreshbit-mappedscreen–CDRAMcanprefetchdatafromDRAMintoSRAMbuffer–SubsequentaccessessolelytoSRAMReading•TheRAMGuide•RDRAM