SystemVerilog硬件设计及建模—第10章

HMECMicroElectronicsCenterSystemVerilog在Verilog语言基础上扩展了“接口”（interface）结构，接口给模型提供了一种新的方式，通过使用接口可以简化大型复杂设计的建模和验证。接口声明接口与模块端口之间的连接接口与模块的区别接口的端口及其方向接口中的任务与函数接口方法的使用接口中的过程块参数化的接口第10章接口HMECMicroElectronicsCenter10.1接口的概念接口反映的是模块与模块之间的互连，对Verilog来说，主要通过模块的端口表现。存储器取指令主处理器测试生成器从处理器Main_busHMECMicroElectronicsCenter10.1接口的概念moduletop(inputwireclock,resetn,teset_mode);wire[15:0]data,address,program_addr,jump_addr;wire[7:0]instr,next_instr;wire[3:0]slave_instr;wireslave_req,slave_rdy;wirebus_req,bus_grant;wiremem_read,mem_write;writedata_rdy;processorproc1(//main_busports.data(data),.address(address),.slave_instr(slave_instr),.slave_req(slave_req),.bus_grant(bus_grant),.mem_read(mem_read),.mem_write(mem_write),.bus_req(bus_req),.slave_rdy(slave_rdy),//otherports.jump_addr(jump_addr),.instr(instr),.clock(clock),.resetn(resetn),.test_mode(test_mode));HMECMicroElectronicsCenter10.1接口的概念slaveslave1(//main_busports.data(data),.address(address),.bus_req(bus_req),.slave_ready(slave_ready),.mem_read(mem_read),.mem_write(mem_write),.slave_instr(slave_instr),.slave_req(slave_req),.bus_grant(bus_grant),.data_rdy(data_rdy),//otherports.clock(clock),.resetn(resetn));dual_port_ramram(//main_busports.data(data),.data_rdy(data_rdy),.address(address),.mem_read(mem_read),.mem_write(mem_write),//otherports.program_addr(program_addr),.data_b(next_instr));HMECMicroElectronicsCenter10.1接口的概念test_generatortest_gen(//main_busports.data(data),.address(address),.mem_read(mem_read),.mem_write(mem_write),//otherports.clock(clock),.resetn(resetn),.test_mode(test_mode));instruction_regir(.program_addr(program_addr),.instr(instr),.jump_addr(jump_addr),.next_instr(next_instr),.clock(clock),.resetn(resetn));endmoduleHMECMicroElectronicsCenter10.1接口的概念moduleprocessor(//main_busportsinoutwire[15:0]data,outputreg[15:0]address,outputreg[3:0]slave_instr,outputregslave_req,outputregbus_grant,outputwiremem_read,outputwiremem_write,inputwirebus_req,inputwireslave_rdy,//otherportsoutputreg[15:0]jump_addr,inputwire[7:0]instr,inputwireclock,inputwireresetn,inputwiretest_mode);...//modulefunctionalitycodeendmodulemoduleslave(//main_busportsinoutwire[15:0]data,inoutwire[15:0]address,outputregbus_req,outputregslave_rdy,outputwiremem_read,outputwiremem_write,inputwire[3:0]slave_instr,inputwireslave_req,inputwirebus_grant,inputwiredata_rdy,//otherportsinputwireclock,inputwireresetn);...//modulefunctionalitycodeendmoduleHMECMicroElectronicsCenter10.1接口的概念moduledual_port_ram(//main_busportsinoutwire[15:0]data,outputwiredata_rdy,inputwire[15:0]address,inputtri0mem_read,inputtri0mem_write,//otherportsinputwire[15:0]program_addr,outputreg[7:0]data_b);...//modulefunctionalitycodeendmodulemoduletest_generator(//main_busportsoutputwire[15:0]data,outputreg[15:0]address,outputregmem_read,outputregmem_write,//otherportsinputwireclock,inputwireresetn,inputwiretest_mode);...//modulefunctionalitycodeendmoduleHMECMicroElectronicsCenter10.1接口的概念moduleinstruction_reg(outputreg[15:0]program_addr,outputreg[7:0]instr,inputwire[15:0]jump_addr,inputwire[7:0]next_instr,inputwireclock,inputwireresetn);...//modulefunctionalitycodeendmoduleHMECMicroElectronicsCenter10.1.1Verilog模块端口的缺点Verilog模块的端口提供了一种描述设计中模块之间连接关系的方式，这种方式直观明了，但在大型复杂设计中，有很多缺点：在多个模块中必须重复声明端口在不同模块中有声明不匹配的风险设计规范中的一个改动需要修改多个模块在多个模块中通信协议也必须重复例如有三个模块对一个共享存储器进行读写操作，那么在这三个模块中，读写操作的控制逻辑必须重复描述限制了抽象的自顶向下的设计用模块端口连接时，设计的具体互连必须在设计周期的早期确定，而不能在一个不需要考虑设计细节的抽象层面上描述。HMECMicroElectronicsCenter10.1.2SystemVerilog接口优势SystemVerilog增加了新的端口类型—接口，接口允许许多信号合成一组由一个端口表示，只需在一个地方对组成接口的信号进行声明，使用这些信号的模块只需一个接口类型的端口。interfacemain_bus;wire[15:0]data;wire[15:0]address;logic[7:0]slave_instr;logicslave_req;logicbus_grant;logicbus_req;logicslave_rdy;logicdata_rdy;logicmem_read;logicmem_write;endinterfaceHMECMicroElectronicsCenter10.1.2SystemVerilog接口优势moduletop(inputlogicclock,resetn,test_mode);logic[15:0]program_addr,jump_addr;logic[7:0]instr,next_instr;main_busbus();//instanceofaninterface//(instancenameisbus)processorproc1(//main_busports.bus(bus),//interfaceconnection//otherports.jump_addr(jump_addr),.instr(instr),.clock(clock),.resetn(resetn),.test_mode(test_mode));HMECMicroElectronicsCenter10.1.2SystemVerilog接口优势slaveslave1(//main_busports.bus(bus),//interfaceconnection//otherports.clock(clock),.resetn(resetn));dual_port_ramram(//main_busports.bus(bus),//interfaceconnection//otherports.program_addr(program_addr),.data_b(next_instr));HMECMicroElectronicsCenter10.1.2SystemVerilog接口优势test_generatortest_gen(//main_busports.bus(bus),//interfaceconnection//otherports.clock(clock),.resetn(resetn),.test_mode(test_mode));instruction_regir(.program_addr(program_addr),.instr(instr),.jump_addr(jump_addr),.next_instr(next_instr),.clock(clock),.resetn(resetn));endmoduleHMECMicroElectronicsCenter10.1.2SystemVerilog接口优势moduleprocessor(//main_businterfaceportmain_busbus,//interfaceport//otherportsoutputlogic[15:0]jump_addr,inputlogic[7:0]instr,inputlogicclock,inputlogicresetn,inputlogictest_mode);...//modulefunctionalitycodeendmodulemoduleslave(//main_businterfaceportmain