A-Half-Rate-Bang-Bang-PhaseFrequency-Detector-for-

AHalf-RateBang-BangPhase/FrequencyDetectorforContinuous-RateCDRCircuitsShao-HungLin,Chang-LinHsiehandShen-luanLiuGraduateInstituteofElectronicsEngineeringandDepartmentofElectricalEngineering,NationalTaiwanUniversity,Taipei,Taiwan10617,R.O.C.Email:[e-mail]-Ahalf-ratebang-bangphaseandfrequencydetectororderloopfilterandthemanuallydigitalcontrolpartare(BBPFD)ispresentedforcontinuous-rateclockanddataplacedoutsidethechiptosaveareaandtomakemeasurementrecovery(CDR)circuits.Theproposedhalf-rateBBPFDnotmoreflexible.onlypreservestheadvantagesofconventionalBBPDs,butFirst,theVCOstartsfromitslowestfrequencyandthealsohastheinfiniteunilateralfrequencydetectionrange.ToBBPFDjudgeswhetherthedatarateisfasterthantheclock.Ifverifytheproposedcircuit,acontinuous-rateCDRcircuitwiththedatarateisfasterthantheclock,theloopfilteristheproposedBBPFDhasbeenfabricatedina0.18umCMOSdischargedtoincreasetheVCO'sfrequency.Thedelaycellprocess.ItcanrecovertheNRZdatawiththebitraterangingforthisVCO[7]isshowninFig.l(b).Ithasninebandstofrom622Mbpsto3.125Gbps.Themeasuredbit-errorrateiscoverthefrequencyrangefrom622MHzto3.125GHz,andlessthan10-12.Thecoreareais0.33x0.27mm2andtheensurestooverlapbetweentheadjacentbands.Whenthedatapowerconsumptionis80mWfroma1.8Vsupply.rateishigherthantheVCO,thenextVCO'sbandischosenandresetVctothesupplyvoltage.ThisfrequencyacquisitionI.INTRODUCTIONprocessisrepeateduntiltheVCO'sfrequencyisclosetotheThelinearandbang-bangphasedetectors(PDs)arewidelydatarate.Whenthefrequencydifferenceissmallenough,theusedinclockanddatarecoverycircuits[1,2].TheoutputBBPDcanaligntherisingedgeoftheVCOwiththecenterofpulseofalinearPDisproportionaltothephaseerror.Itwillthedata.Sincethishalf-rateBBPFDneedsthequadraturehavelessjitter,butthespeedislimitedinmulti-Gb/sclocks,henceamaster-slavedivide-by-twodividerisusedtoapplications.Ontheotherhand,thebang-bangPD[2]hasageneratethequadratureclocks,CKIandCKQ.higherspeedatthecostoftheworsejitterperformanceduetoDemuxedr---------itsbang-bangnature.Remuxed:Of-chip------InordertolowertheVCOfrequency,ahalf-rateBBPDisData'-cartupdesired.Ahalf-rateBBPDhasbeenpresentedin[3],whichisNRZIccomposedofthreedouble-edge-triggeredflipflops(DETFFs),Half-RatebutitdoesnotassumeatristateoutputintheabsenceofdataaBBPFD-Rt4transition.HencetheloopbandwidthmustbedesignedManualcarefullytoensuretheVCOfrequencydoesnotdrifttoomuch.ciControlFrequencydetector(FD)isalsoanimportantcomponentinaCDRcircuit,especiallyforcontinuous-rateCDRcircuits..-,ThePD'sfrequencylockingrangecomparedtoVCO'stuningCKI&CKQ12rangeisquitesmallandneedssomeauxiliaryfrequencylIacquisitioncircuits.TheFDin[3]andquadraturefrequencyFig.1(a)Thecontinuous-rateCDRcircuitsdetectors(QFD)[4,5],whichonlyhavelimitedfrequencylockingrange,arenotsuitableincontinuous-rateCDRcircuitsbecausetheharmoniclockingmayoccur.Toextendthelxlx3x3x3x3xlxlxfrequencyacquisitionrange,theunilateralwide-rangeFDisDlo]D20]D30]D40]Vco][oVc[oD4oD3[oD2koDlpresentedin[6].Similarly,itneedsacomplexcircuitryandMD1MD2MD3MD4MCMMMCMD4MD3MD2MDImayhaveahighpower,largearea,andextracapacitanceloadOutOut+fortheVCO.In+o]MN+M-oIn-Inthispaper,ahalf-ratebang-bangPFDispresented.TheproposedBBPFDovercomestheaboveissuesanditissuitableT1forcontinuous-rateCDRcircuits.MNCII.CIRCUITDESCRIPTIONFig.1(b)Thedigitally-controlledVCO[7]Theproposedcontinuous-rateCDRcircuitisshowninFig.1(a).Itiscomposedoftheproposedhalf-rateBBPFD,awideTheproposedBBPFDisshowninFig.2.ItiscomposedoftuningrangeVCO,adivide-by-twodividerandtwochargefourDETFFs,twoXORgatesandoneANDgate.EachpumpcircuitsoneforPDandtheotherforFD.Thesecond-1-4244-0637-4/07/$20.OO©C2007IEEE353DETFFconsistsoftwoD-latchesandamultiplexer.Theconsecutivelysampleddata,(Aprevious,Bprevious,Apresent)oroperationprincipleofthisBBPFDisdescribedasfollows.(Bprevious,Aprevious,Bpresent),maybe(010)or(101).Then,twodataAlCpulses,XandY,overlappedwithTCKI/4occur.Thus,onecanoDQ-DlQapplythebothpulses,XandY,toanANDgateandtheoutput,CKIc.-CIkCKQ.~--cikXFD_out,willbehigh.Itindicatesthattheclockistooslow;i.e,.L___j.1.FD_outonehastospeeduptheclock.However,ifthedatarateisTclk/4delayequaltoorslowerthantheclock,thepulses,XandY,areseparatedandthereisnooverlappedtimebetweenthem.Hence,theoutput,FD_out,willbelow.DQBhaTheadvantagesofthisproposedBBFDislistedasfollows.CKQDCIkCKIokD\First,itiscomposedofonlyanANDgateinsteadofthe.__J.\cikcomplexfinitestatemachinein[7,8].Second,itaddsasmall\Tcik/4delayL,'LQcapacitanceloadtotheclockbuffer.Inahigh-speedCDRCikcircuit,theclockbufferconsumesalargepowerinordertoCikdrivethePDandtheFD.Finally,comparedwiththeFig.2Proposedhalf-rateBBPFDtraditionalFDs[7,8],itoutputsapulsewiththepulsewidthofTCKI/4ItresultsinthegainoftheBBFDindependentofthedatadatadatapattern[6].CKICKIdataCKQCKQA.ACKIj..-[_CBmB-C-----I--CKQJlJlJlJLDFDAx_________xY--yBFDOoutFDoutCFig.3TheleftfigureshowsthetimingdiagramfortheearlyclockandtherightoneshowsthetimingdiagramforthelateDclock.Forbothcases,thedatarateisequaltotheclock.xA.Theoperationofhalf-rateBBPDyThetimingdiagramsfortheearlyandlateclocksareFD_