《VHDL实用教程》完整版【汉语版】-9第七章

KONXINKONXIN7VHDL1537VHDLVHDLVHDLRTLRTLVHDL§7.1VHDL7-18VHDL7-28ABEL-HDL7-1LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALLENTITYcunter_upISPORT(reset,clock:INSTD_LOGIC;counter:OUTSTD_LOGIC_VECTOR(7DOWNTO0));END;ARCHITECTUREbehvofcunter_upISVHDL154SIGNALcnt_ff:UNSIGNED(7DOWNTO0);BEGINPROCESS(clock,reset,cnt_ff)BEGINIFreset='1'THENcnt_ff=X00;ELSIF(clock='1'ANDclock'EVENT)THENcnt_ff=cnt_ff+1;ENDIF;ENDPROCESS;counter=STD_LOGIC_VECTOR(cnt_ff);ENDARCHITECTUREbehv7-2MODULEcounter_upClock,reset,PIN;Counter7..counter0PINISTYPE'COM';Cnt_ff7..cnt_ff0NODEISTYPE'REG';Counter=[counter7..counter0];Cnt=[cnt_ff7..cnt_ff0];EQUATIONSCnt.CLK=clock;Cnt.AR=reset;Cnt:=cnt.FB+1;Counter=cnt;ENDcounter_up7-17-287-2ABEL-HDL8'REG'8'COM'cnt.CLK=clcokCLKcnt8clockcnt.AR=resetresetcntARcnt:=cnt.FB+1.FB1cnt7-2PLDABEL7-1KONXINKONXIN7VHDL155ABEL-HDLELSIF(clock='1'ANDclock’EVENT)THENVHDLVHDL7-2cnt.CLK=clockABEL-HDLVHDLVHDLVHDLVHDLVHDLVHDLVerilog-HDLRTLVHDLVHDLVHDLVHDLVHDLVHDLCadenceSynplicitySynopsysViewlogicEDAVHDL§7.2RTLRTLRTLVHDLRTLVHDL1567-37-3ENTITY\74LS18\ISPORT(I0_A,I0_B,I1_A,I1_B,I2_A:INSTD_LOGIC;I2_BI3_AI3_B:INSTD_LOGIC;O_A:OUTSTD_LOGIC;O_B:OUTSTD_LOGIC);END\74LS18\;ARCHITECTUREmodelOF\74LS18\ISBEGINO_A=NOT(I0_AANDI1_AANDI2_AANDI3_A)AFTER55ns;O_B=NOT(I0_BANDI1_BANDI2_BANDI3_B)AFTER55ns;ENDmodel;§7.3VHDL•••VHDLVHDL7-4ARCHITECTURESTRUCTUREOFCOUNTER3ISCOMPONENTDFFPORT(CLK,DATA:INBIT;Q:OUTBIT);ENDCOMPONENT;COMPONENTAND2PORT(I1,I2:INBIT;O:OUTBIT);ENDCOMPONENT;COMPONENTOR2PORT(I1,I2:INBIT;O:OUTBIT);KONXINKONXIN7VHDL157ENDCOMPONENT;COMPONENTNAND2PORT(I1,I2:INBIT;O:OUTBIT);ENDCOMPONENT;COMPONENTXNOR2PORT(I1,I2:INBIT;O:OUTBIT);ENDCOMPONENT;COMPONENTINVPORT(I:INBIT;O:OUTBIT);ENDCOMPONENT;SIGNALN1,N2,N3,N4,N5,N6,N7,N8,N9:BIT;BEGINu1:DFFPORTMAP(CLK,N1,N2);u2:DFFPORTMAP(CLK,N5,N3);u3:DFFPORTMAP(CLK,N9,N4);u4:INVPORTMAP(N2,N1);u5:OR2PORTMAP(N3,N1,N6);u6:NAND2PORTMAP(N1,N3,N7);u7:NAND2PORTMAP(N6,N7,N5);u8:XNOR2PORTMAP(N8,N4,N9);u9:NAND2PORTMAP(N2,N3,N8);COUNT(0)=N2;COUNT(1)=N3;COUNT(2)=N4;ENDSTRUCTURE;VHDLVHDLVHDLEDAEDAVHDLEDAEDAVHDL7-1VHDL7-2VHDL7-3VHDL7-428