《VHDL实用教程》完整版【汉语版】-4第二章

KONXINKONXINVHDL122VHDLVHDL§2.1VHDL1212-121absys0yas1ybVHDL2-1LIBRARYIEEE;IEEEUSEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21ISmux21PORT(ab:INSTD_LOGIC;PORTs:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux21;mux21ARCHITECTUREoneOFmux21ISBEGINy=aWHENs='0'ELSEbWHENs='1';ENDARCHITECTUREone;21VHDLVHDLEDIFALTERAEPM7128S2-1EPM7128S2-121mux212VHDL13HARDWAREDEBUGEDAMUX+PLUSII(12)VHDLmux214absyMUX+PLUSII2-1FPGACPLD2-121mux2121VHDLVHDL(1)(LIBRARY)IEEESTD_LOGIC_1164VHDLVHDL(2)(ENTITY)mux21mux21absyPORTmux21PORTINababOUTyabsyIEEESTD_LOGIC_1164STD_LOGIC(3)(ARCHITECTURE)mux21=y=aa()y2-1ENDENTITYmux21ENDARCHITECTUREoneVHDLIEEESTD1076_1993VHDL’87IEEESTD1076_1987ENDmux21ENDoneEDAVHDLVHDL'87VHDLVHDL’87VHDLVHDLIEEEKONXINKONXINVHDL142-1VHDLVHDL2.22.3VHDL2-1VHDLVHDLVHDLVHDL2-13HDL21VHDL2-2DENAENAQ2-2VHDL2-2LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYLatchISPORTD:INSTD_LOGIC;ENA:INSTD_LOGIC;Q:OUTSTD_LOGIC);1ENDENTITYLatchARCHITECTUREoneOFLatchISSIGNALsig_save:STD_LOGIC;BEGINPROCESS(D,ENA)BEGINIFENA='1'THENsig_save=D;ENDIF;Q=sig_save;ENDPROCESS;ENDARCHITECTUREone;2-11(1)SIGNALSIGNALsig_save2-212VHDL15D(2)PROCESS(D,ENA)àENDPROCESSDENA(VHDL)ENADsig_savesig_saveQENAsig_saveQIF_THENVHDLIFsig_save=DENDIFIF_THENPROCESSVHDLVHDLPROCESS(DENA)(DENA)DENA()()VHDL2-12-2VHDLVHDL2-12-2ABELCOMREG§2.2VHDL112-31absocoh_adder2-42-4f_adder3u1u2u32-3VHDL2-4VHDLEDA2-31KONXINKONXINVHDL162-3--LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYor2ISPORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDENTITYor2ARCHITECTUREfu1OFor2ISBEGINc=aORb;ENDARCHITECTUREfu1;--LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYh_adderISPORT(ab:INSTD_LOGIC;co,so:OUTSTD_LOGIC);ENDENTITYh_adderARCHITECTUREfh1OFh_adderISBEGINso=(aORb)AND(aNANDb);co=NOT(aNANDb);ENDARCHITECTUREfh1;--1LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYf_adderISPORT(ainbincin:INSTD_LOGIC;coutsum:OUTSTD_LOGIC);ENDENTITYf_adder;ARCHITECTUREfd1OFf_adderISCOMPONENTh_adderPORT(ab:INSTD_LOGIC;coso:OUTSTD_LOGIC);ENDCOMPONENTCOMPONENTor2PORT(ab:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDCOMPONENTSIGNALdef:STD_LOGIC;BEGINu1:h_adderPORTMAP(a=ainb=binco=dso=e);u2:h_adderPORTMAP(a=eb=cinco=fso=sum);u3:or2PORTMAP(a=db=fc=cout);ENDARCHITECTUREfd1;,2-3EDA2-33VHDL2f_adderVHDLor2.vhdh_adder.vhdf_adder.vhd2-3(1)--VHDL--(2)or2or2ab()c()2VHDL17abc(3)h_adderfh12-3(2-1)VHDLNANDNOTORAND(4)VHDL2-41f_adderainbincincoutsum1fd1COMPONENTCOMPONENTor2h_adder2-42-22-1H_ADDERaBsoco00000110101011012-2F_ADDERainBincinCoutsum0000000101010010111010001101101101011111(5)fd1COMPONENTàENDCOMPONENT(ComponentDeclaration)SIGNAL2-41KONXINKONXINVHDL18defPORTMAP()(ComponentInstantiation)MAPu2h_adderabcosoecinfsum=(6)2-3f_adderIEEEIEEE.STD_LOGIC_1164.ALLVHDLVHDLVHDL2-5WORKVHDL32-5VHDL2-5VHDLENTITYARCHITECTURECONFIGURATION