《VHDL实用教程》完整版【汉语版】-10第八章

KONXINKONXINVHDL1588SimulationVHDLVHDLEDAFPGAVHDLVHDLVHDLVHDLEDASRAMFPGAVHDLVHDLVHDL1213§8.1VHDLVHDLEDA8159VHDLVHDLVHDLVHDLVHDLVHDL(1)DEBUGModelSimActive-VHDLVHDL(2)CVHDL8-18-1VHDLVHDLVHDLVHDLVHDLMentorGraphicsRenoirXilinxFoundationSeriesEDAVHDLVHDLVHDLVHDLVHDLKONXINKONXINVHDL160VHDLVHDLLIBRARYUSEVHDLVHDLVHDLFPGA/CPLDPLDVHDLVHDLVHDLVHDLVHDLVHDLVHDLREPORTASSERTVHDLEDAVHDLVHDLMAX+PLUSIISNFPCVHDLModelTechnologyModelSimAldecActive-VHDLModelSimV-System/WindowsWindows8-1VHDLEDAMAX+PLUSIIEPF10K10LC84MAX+PLUSIISNFVHDL8-2EPF10K10LC848-2VHDL8-1LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYand1ISPORT(aaa,bbb:INSTD_LOGIC;ccc:OUTSTD_LOGIC);ENDand1;ARCHITECTUREoneOFand1ISBEGINccc=aaaANDbbb;END;81618-2LIBRARYIEEE;USEIEEE.std_logic_1164.all;ENTITYTRIBUF_and1ISGENERIC(ttri:TIME:=1ns;ttxz:TIME:=1ns;ttzx:TIME:=1ns);PORT(in1:INstd_logic;oe:INstd_logic;y:OUTstd_logic);ENDTRIBUF_and1;ARCHITECTUREbehaviorOFTRIBUF_and1ISBEGINPROCESS(in1,oe)BEGINIFoe'EVENTTHENIFoe='0'THENy=TRANSPORT'Z'AFTERttxz;ELSIFoe='1'THENy=TRANSPORTin1AFTERttzx;ENDIF;ELSIFoe='1'THENy=TRANSPORTin1AFTERttri;ELSIFoe='0'THENy=TRANSPORT'Z'AFTERttxz;ENDIF;ENDPROCESS;ENDbehavior;LIBRARYIEEE;USEIEEE.std_logic_1164.all;USEwork.tribuf_and1;ENTITYand1ISPORT(aaa:INstd_logic;bbb:INstd_logic;ccc:OUTstd_logic);ENDand1;ARCHITECTUREEPF10K10LC84_a3OFand1ISSIGNALgnd:std_logic;SIGNALvcc:std_logic;SIGNALn_8,n_9,n_10,n_11,n_12,a_a4_aOUT,n_14,n_15,n_16,n_17,n_18,n_20,n_22:std_logic;COMPONENTTRIBUF_and1GENERIC(ttri,ttxz,ttzx:TIME);PORT(in1,oe:INstd_logic;y:OUTstd_logic);ENDCOMPONENT;BEGINKONXINKONXINVHDL162gnd='0';vcc='1';PROCESS(aaa,bbb)BEGINASSERTaaa/='X'ORNow=0nsREPORTUnknownvalueonaaaSEVERITYWarning;ASSERTbbb/='X'ORNow=0nsREPORTUnknownvalueonbbbSEVERITYWarning;ENDPROCESS;TRIBUF_2:TRIBUF_and1GENERICMAP(ttri=2600ps,ttxz=4500ps,ttzx=4500ps)PORTMAP(IN1=n_8,OE=vcc,Y=ccc);DELAY_3:n_8=TRANSPORTn_9;XOR2_4:n_9=n_10XORn_14;OR1_5:n_10=n_11;AND1_6:n_11=n_12;DELAY_7:n_12=TRANSPORTa_a4_aOUTAFTER2500ps;AND1_8:n_14=gnd;DELAY_9:a_a4_aOUT=TRANSPORTn_15AFTER500ps;XOR2_10:n_15=n_16XORn_22;OR1_11:n_16=n_17;AND2_12:n_17=n_18ANDn_20;DELAY_13:n_18=TRANSPORTbbbAFTER4800ps;DELAY_14:n_20=TRANSPORTaaaAFTER4300ps;AND1_15:n_22=gnd;ENDEPF10K10LC84_a3;VHDLVHDLVHDL§8.2VHDLVHDLFPGA/CPLDVHDLFPGA/CPLDFPGA/CPLDVHDL8-2VHDL81638.2.1VHDLδδVHDLVHDLδVHDLz=xXORyAFTER5ns5nsxXORy5nsxXORy5nszxyz=xXORyxXORyδzFPGA/CPLDVHDL8.2.2VHDLPCBASICz=TRANSPORTxAFTER10ns;TRANSPORTKONXINKONXINVHDL164AFTER§8.3dVHDLδδδδ§8.4VHDLTEXTIOVHDL44LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYADDER4ISPORT(a,b:ININTEGERRANGE0TO15;c:OUTINTEGERRANGE0TO15);ENDADDER4;ARCHITECTUREoneOFADDER4ISBEGINc=a+b;ENDone;8165hVHDLENTITYSIGGENISPORT(sig1:OUTINTEGERRANGE0TO15;sig2:OUTINTEGERRANGE0TO15);END;ARCHITECTURESimOFSIGGENISBEGINsig1=10,5AFTER200ns,8AFTER400ns;sig2=3,4AFTER100ns,6AFTER300ns;END;8-2ModelSimSIGGENADDER4VHDL8-2SIGGENENTITYBENCHISEND;ARCHITECTUREoneOFBENCHISCOMPONENTADDER4PORT(a,b:integerrange0to15;c:OUTINTEGERRANGE0TO15);ENDCOMPONENT;COMPONENTSIGGENPORT(sig1:OUTINTEGERRANGE0TO15;sig2:OUTINTEGERRANGE0TO15);ENDCOMPONENT;SIGNALa,b,c:INTEGERRANGE0TO15;BEGINU1:ADDER4PORTMAP(a,b,c);U2:SIGGENPORTMAP(sig1=a,sig2=b);END;abcModelSim8-3hKONXINKONXINVHDL166ModelSimforceforceforce[][,][-repeat]8-3BENCHforcea00forceb00,110b00101forceclk00,115–repeat20clk20ADDER4ModelSimforcea100,5200,8400forceb30,4100,6300RunRun5008-3ModelSim12VHDL§8.5VHDLVHDLTestBenchVHDLVHDLVHDLVHDLVHDLVHDLVHDLVHDLVHDLTestBenchVHDL/81678.4VHDLVHDL8LibraryIEEE;useIEEE.std_logic_1164.all;entitycounter8isportCLKCELOADDIRRESET:inSTD_LOGIC;DIN:inINTEGERrange0to255;COUNT:outINTEGERrange0to255);endcounter8;architecturecounter8_archofcounter8isbeginprocess(CLK,RESET)variableCOUNTER:INTEGERrange0to255;beginifRESET='1'thenCOUNTER:=0;elsifCLK='1'andCLK'eventthenifLOAD='1'thenCOUNTER:=DIN;ElseifCE='1'thenifDIR='1'thenifCOUNTER=255thenCOUNTER:=0;ElseCOUNTER:=COUNTER+1;endif;elseifCOUNTER=0thenCOUNTER:=255;ElseCOUNTER:=COUNTER-1;endif;endif;endif;endif;endif;COUNT=COUNTER;endprocess;endcounter8_arch;Entitytestbenchisendtestbench;Architecturetestbench_archoftestbenchisFileRESULTS:TEXTopenWRITE_MODEisresults.txt;Componentcounter8port(CLK:inSTD_LOGIC;RESET:inSTD_LOGIC;CE,LOAD,DIR:inSTD_LOGIC;DIN:inINTEGERrange0to255;COUNT:outINTEGERrange0to255);KONXINKONXINVHDL168endcomponent;sharedvariableend_sim:BOOLEAN:=false;signalCLK,RESET,CE,LOAD,DIR:STD_LOGIC;signalDIN:INTEGERrange0to255;signalCOUNT:INTEGERrange0to255;procedureWRITE_RESULTS(CLKCELOADLOADRESET:STD_LOGIC;DINCOUNT:INTEGER)isVariableV_OUT:LINE;Beginwrite(V_OUT,now,right,16,ps);--write(V_OUT,CLK,right,2);write(V_OUT,RESET,right,2);write(V_OUT,CE,right,2);write(V_OUT,LOAD,right,2);write(V_OUT,DIR,right,2);write(V_OUT,DIN,right,257);--writeoutputswrite(V_OUT,COUNT,right,257);writeline(RESULTS,V_OUT);endWRITE_RESULTS;beginUUT:COUNTER8portmap(CLK=CLK,RESET=RESET,CE=CE,LOAD=LOAD,DIR=DIR,DIN=DIN,COUNT=COUNT);CLK_IN:processBeginifend_sim=falsethenCLK='0';Waitfor15ns;CLk='1';Waitfor15ns;ElseWait;endif;endprocess;