ATmega64A-AU

Features•High-performance,Low-powerAVR®8-bitMicrocontroller�AdvancedRISCArchitecture–130PowerfulInstructions–MostSingleClockCycleExecution–32x8GeneralPurposeWorkingRegisters+PeripheralControlRegisters–FullyStaticOperation–Upto16MIPSThroughputat16MHz–On-chip2-cycleMultiplier�HighEnduranceNon-volatileMemorysegments–64KBytesofIn-SystemReprogrammableFlashprogrammemory–2KBytesEEPROM–4KBytesInternalSRAM–Write/EraseCycles:10,000Flash/100,000EEPROM–Dataretention:20yearsat85°C/100yearsat25°C(1)–OptionalBootCodeSectionwithIndependentLockBits�In-SystemProgrammingbyOn-chipBootProgram�TrueRead-While-WriteOperation–Upto64KBytesOptionalExternalMemorySpace–ProgrammingLockforSoftwareSecurity–SPIInterfaceforIn-SystemProgramming�JTAG(IEEEstd.1149.1Compliant)Interface–Boundary-scanCapabilitiesAccordingtotheJTAGStandard–ExtensiveOn-chipDebugSupport–ProgrammingofFlash,EEPROM,Fuses,andLockBitsthroughtheJTAGInterface�PeripheralFeatures–Two8-bitTimer/CounterswithSeparatePrescalersandCompareModes–TwoExpanded16-bitTimer/CounterswithSeparatePrescaler,CompareMode,andCaptureMode–RealTimeCounterwithSeparateOscillator–Two8-bitPWMChannels–6PWMChannelswithProgrammableResolutionfrom1to16Bits–8-channel,10-bitADC�8Single-endedChannels�7DifferentialChannels�2DifferentialChannelswithProgrammableGain(1x,10x,200x)–Byte-orientedTwo-wireSerialInterface–DualProgrammableSerialUSARTs–Master/SlaveSPISerialInterface–ProgrammableWatchdogTimerwithOn-chipOscillator–On-chipAnalogComparator�SpecialMicrocontrollerFeatures–Power-onResetandProgrammableBrown-outDetection–InternalCalibratedRCOscillator–ExternalandInternalInterruptSources–SixSleepModes:Idle,ADCNoiseReduction,Power-save,Power-down,StandbyandExtendedStandby–SoftwareSelectableClockFrequency–ATmega103CompatibilityModeSelectedbyaFuse–GlobalPull-upDisable�I/OandPackages–53ProgrammableI/OLines–64-leadTQFPand64-padQFN/MLF�OperatingVoltages–2.7-5.5VforATmega64A�SpeedGrades–0-16MHzforATmega64A8-bitMicrocontrollerwith64KBytesIn-SystemProgrammableFlashATmega64A8160C–AVR–07/0928160C–AVR–07/09ATmega64A1.PinConfigurationFigure1-1.PinoutATmega64ANote:ThebottompadundertheQFN/MLFpackageshouldbesolderedtoground.1234567891011121314151648474645444342414039383736353433PENRXD0/(PDI)PE0(TXD0/PDO)PE1(XCK0/AIN0)PE2(OC3A/AIN1)PE3(OC3B/INT4)PE4(OC3C/INT5)PE5(T3/INT6)PE6(ICP3/INT7)PE7(SS)PB0(SCK)PB1(MOSI)PB2(MISO)PB3(OC0)PB4(OC1A)PB5(OC1B)PB6PA3(AD3)PA4(AD4)PA5(AD5)PA6(AD6)PA7(AD7)PG2(ALE)PC7(A15)PC6(A14)PC5(A13)PC4(A12)PC3(A11)PC2(A10PC1(A9)PC0(A8)PG1(RD)PG0(WR)6463626160595857565554535251504917181920212223242526272829303132(OC2/OC1C)PB7TOSC2/PG3TOSC1/PG4RESETVCCGNDXTAL2XTAL1(SCL/INT0)PD0(SDA/INT1)PD1(RXD1/INT2)PD2(TXD1/INT3)PD3(ICP1)PD4(XCK1)PD5(T1)PD6(T2)PD7AVCCGNDAREFPF0(ADC0)PF1(ADC1)PF2(ADC2)PF3(ADC3)PF4(ADC4/TCK)PF5(ADC5/TMS)PF6(ADC6/TDO)PF7(ADC7/TDI)GNDVCCPA0(AD0)PA1(AD1)PA2(AD2)TQFP/MLF38160C–AVR–07/09ATmega64A2.OverviewTheATmega64Aisalow-powerCMOS8-bitmicrocontrollerbasedontheAVRenhancedRISCarchitecture.Byexecutingpowerfulinstructionsinasingleclockcycle,theATmega64Aachievesthroughputsapproaching1MIPSperMHz,allowingthesystemdesignertooptimizepowercon-sumptionversusprocessingspeed.2.1BlockDiagramFigure2-1.BlockDiagramTheAVRcorecombinesarichinstructionsetwith32generalpurposeworkingregisters.Allthe32registersaredirectlyconnectedtotheArithmeticLogicUnit(ALU),allowingtwoindependentregisterstobeaccessedinonesingleinstructionexecutedinoneclockcycle.Theresultingarchitectureismorecodeefficientwhileachievingthroughputsuptotentimesfasterthancon-ventionalCISCmicrocontrollers.TheATmega64Aprovidesthefollowingfeatures:64KbytesofIn-SystemProgrammableFlashwithRead-While-Writecapabilities,2KbytesEEPROM,4KbytesSRAM,53generalpurposeI/OPROGRAMCOUNTERINTERNALOSCILLATORWATCHDOGTIMERSTACKPOINTERPROGRAMFLASHMCUCONTROLREGISTERSRAMGENERALPURPOSEREGISTERSINSTRUCTIONREGISTERTIMER/COUNTERSINSTRUCTIONDECODERDATADIR.REG.PORTBDATADIR.REG.PORTEDATADIR.REG.PORTADATADIR.REG.PORTDDATAREGISTERPORTBDATAREGISTERPORTEDATAREGISTERPORTADATAREGISTERPORTDTIMINGANDCONTROLOSCILLATOROSCILLATORINTERRUPTUNITEEPROMSPIUSART0STATUSREGISTERZYXALUPORTBDRIVERSPORTEDRIVERSPORTADRIVERSPORTFDRIVERSPORTDDRIVERSPORTCDRIVERSPB0-PB7PE0-PE7PA0-PA7PF0-PF7RESETVCCGNDAREFXTAL1XTAL2CONTROLLINES+-ANALOGCOMPARATORPC0-PC78-BITDATABUSAVCCUSART1CALIB.OSCDATADIR.REG.PORTCDATAREGISTERPORTCON-CHIPDEBUGJTAGTAPPROGRAMMINGLOGICPENBOUNDARY-SCANDATADIR.REG.PORTFDATAREGISTERPORTFADCPD0-PD7DATADIR.REG.PORTGDATAREG.PORTGPORTGDRIVERSPG0-PG42-WIRESERIALINTERFACE48160C–AVR–07/09ATmega64Alines,32generalpurposeworkingregisters,RealTimeCounter(RTC),fourflexibleTimer/Coun-terswithcomparemodesandPWM,twoUSARTs,abyteorientedTwo-wireSerialInterface,an8-channel,10-bitADCwithoptionaldifferentialinputstagewithprogrammablegain,program-mableWatchdogTimerwithinternalOscillator,anSPIserialport,IEEEstd.1149.1compliantJTAGtestinterface,alsousedforaccessingtheOn-chipDebugsystemandprogramming,andsixsoftwareselectablepowersavingmodes.TheIdlemodestopstheCPUwhileallowingtheSRAM,Timer/Counters,SPIport,andinterruptsystemtocont