GL85X Design Guide(E)_201

USB2.0High-SpeedHUBControllerDesignGuideRevision2.01Oct.14,2010GenesysLogic,Inc.USB2.0HubDesignGuide©2010GenesysLogic,Inc.-Allrightsreserved.Page2CopyrightCopyright©2010GenesysLogic,Inc.Allrightsreserved.NopartofthematerialsshallbereproducedinanyformorbyanymeanswithoutpriorwrittenconsentofGenesysLogic,Inc.OwnershipandTitleGenesysLogic,Inc.ownsandretainsofitsright,titleandinterestinandtoallmaterialsprovidedherein.GenesysLogic,Inc.reservesallrights,including,butnotlimitedto,allpatentrights,trademarks,copyrightsandanyotherproprietyrights.Nolicenseisgrantedhereunder.DisclaimerAllMaterialsareprovided“asis”.GenesysLogic,Inc.makesnowarranties,express,impliedorotherwise,regardingtheiraccuracy,merchantability,fitnessforanyparticularpurpose,andnon-infringementofintellectualproperty.InnoeventshallGenesysLogic,Inc.beliableforanydamages,including,withoutlimitation,anydirect,indirect,consequential,orincidentaldamages.Thematerialsmaycontainerrorsoromissions.GenesysLogic,Inc.maymakechangestothematerialsortotheproductsdescribedhereinatanytimewithoutnotice.GenesysLogic,Inc.12F,No.205,Sec.3,BeishinRd.,ShindianCity,Taipei,TaiwanTel:(886-2)8913-1888Fax:[phone]©2010GenesysLogic,Inc.-Allrightsreserved.Page3RevisionHistoryRevisionDateDescription1.0007/03/2003Firstformalrelease1.1010/29/2003ChangelargecontentsinCh1~Ch61.1103/23/2004Addnoticeitem7inCh61.1202/22/2005AddGL850A1.5007/13/2005AddGL852,removeGL8501.6011/13/2006ModifyX’tal.1.7011/29/2006ModifyFigure31.8008/31/2009Modify2.1,2.3,p.6-7Add2.4,2.5,p.7-8ModifyCh4,Ch5,p.11-121.9012/17/2009Modify2.1,p.6Add2.6,p.9ModifyCh5,p.132.0001/26/2010Add5.6,p.132.0110/14/2010Modify5.6,p.13USB2.0HubDesignGuide©2010GenesysLogic,Inc.-Allrightsreserved.Page4TableofContents1.PREFACE.............................................................................................................................52.GENERALOFTHEUSB2.0HIGHSPEEDSIGNALALLOCATION........................62.1CircuitryRoutingandComponentPlacementofthe4-LayerPCB.........................62.2RoutingandPlacingofComponentson2-LayerPCB...............................................72.3LayoutofD+,D-............................................................................................................72.4TheCompletenessofGND............................................................................................82.5PowerTrace...................................................................................................................82.6CrystalRoutingandPlacement...................................................................................93.LAYOUTDIAGRAM........................................................................................................103.1SingleSidePlacement..................................................................................................103.2PlacementontheBothSides.......................................................................................113.3DifferentialSignalSourceTraces(D+,D-)...............................................................114.GROUNDINGANDPOWERLAYOUT.........................................................................125.SPECIALNOTES..............................................................................................................13USB2.0HubDesignGuide©2010GenesysLogic,Inc.-Allrightsreserved.Page51.PREFACEThepurposeofthisdocumentistoprovidesuggestionsanddescriptionsforthedesignofPCBlayoutaboutUSB2.0High-SpeedHubControllerofGenesysLogicInc.,sothattheclientcanverifyintheshortesttimeandstartmassproduction.USB2.0HubDesignGuide©2010GenesysLogic,Inc.-Allrightsreserved.Page62.GENERALOFTHEUSB2.0HIGHSPEEDSIGNALALLOCATION2.1CircuitryRoutingandComponentPlacementofthe4-LayerPCB1.Use4-layerPCB:1stLayerforcomponentplacementandsignallayout,2ndLayer:GND,3rdLayer:Power,and4thLayer:layoutofsignallines.LayerDescriptionLayer1SignalLayer1Layer2GroundLayer3PowerLayer4SignalLayer2RoutingofUSB2.0D+/D-datasignalshallbeonSignallayer12.FirstlyplaceX’talandD+&D-write;theymustbeofequallength,parallelandequalspacing.3.NowireisallowedunderneaththeX’tal.X’talistobeasneartheICaspossible.ThemaximumsuggesteddistancebetweenX’taltraceandtheICis1cm.4.BothsidesofX’talIN/OUTleadsshallbeenvelopedbyGNDtoavoidnoiseinterference.(Fig.3.2)5.EnlargethePowerTraceofupstreamportanddownstreamporttoatleast50mil.Ifpunch-throughholeisrequiredtoconnectthepackface,usemultipleholestoavoidvoltagedrop.Takespecialattentiononthis,forvoltagedropisverifiedatUSB-IFLogocertification.Unsteadyvoltagecausessignaltojitterseverelyandthusfailureofcompatibilitytest.6.Allwiresshallnothave90-degreeturns.Ifsuchturnsareinevitable,makeanarcordouble45°toreplacethem,seeFig.2.1.ItwillhelptominimizetheEMIproblems.Figure2.1USB2.0HubDesignGuide©2010GenesysLogic,Inc.-Allrightsreserved.Page77.ForbidanyPowerTraceorClockLinetopassunderneathaChip.8.AllBeadsaretobeplacedasneartotheUSBconnectoraspossible.9.AllbypassandelectrolyticcapacitorsaretobeplacedasneartheICaspos