TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS

TN-47-01DDR2DESIGNGUIDEFORTWO-DIMMSYSTEMSOverview09005aef80cc3dceMicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.TN_47_01.fm-Rev.B12/09EN1©2005MicronTechnology,Inc.Allrightsreserved.ProductsandspecificationsdiscussedhereinareforevaluationandreferencepurposesonlyandaresubjecttochangebyMicronwithoutnotice.ProductsareonlywarrantedbyMicrontomeetMicron’sproductiondatasheetspecifications.Allinformationdiscussedhereinisprovidedonan“asis”basis,withoutwarrantiesofanykind.ProductsandspecificationsdiscussedhereinaresubjecttochangebyMicronwithoutnotice.TechnicalNoteDDR2-533MemoryDesignGuideforTwo-DIMMUnbufferedSystemsOverviewDDR2memorybussesvarydependingontheintendedmarketforthefinishedproduct.SomeproductsmustsupportfourormoreregisteredDIMMs,whilesomearepoint-to-pointtopologies.ThisdocumentfocusesonsolutionsrequiringtwounbufferedDIMMsoperatingatadatarateof533megabitspersecond(Mb/s)andisintendedtoassistboarddesignerswiththedevelopmentandimplementationoftheirproducts.Thedocumentconsistsoftwosections.ThefirstsectionusesdatagatheredfromachipsetandmotherboarddesignedbyMicrontoprovideasetofboard-designrules.Theserulesaremeanttobeastartingpointforaboarddesign.Thesecondsectiondetailstheprocessofdeterminingtheportionofthetotaltimingbudgetallottedtotheboardinterconnect.Theintentisthatboarddesignerswillusethefirstsectiontodevelopasetofgeneralrulesandthen,throughsimulation,verifythedesignintheirparticularenvironments.IntroductionSystemsusingunbufferedDIMMscanimplementtheaddressandcommandbususingvariousconfigurations.Forexample,somecontrollershavetwocopiesoftheaddressandcommandbus,sothesystemcanhaveoneortwoDIMMspercopy,butnevermorethantwoDIMMstotal.Further,theaddressbuscanbeclockedusing1Tor2Tclocking.With1T,anewcommandcanbeissuedoneveryclockcycle.2Ttimingwillholdtheaddressandcommandbusvalidfortwoclockcycles.Thisreducestheefficiencyofthebustoonecommandpertwoclocks,butitdoublestheamountofsetupandholdtime.Thedatabusremainsthesameforallofthevariationsintheaddressbus.ThisdesignguidecoversaDDR2systemusingtwounbufferedDIMMs,operatingata533Mb/sdatarateandtwovariationsoftheaddressandcommandbus.Thefirstvaria-tioncoveredisasystemwithoneDIMMpercopyoftheaddressandcommandbususing1Tclocking.AblockdiagramofthistopologyisshowninFigure1onpage2.ThesecondvariationisasystemwithtwoDIMMsontheaddressandcommandbususing2Tclockingtopology,asshowninFigure2onpage3.Pleasenotethattheguidelinesprovidedinthissectionareintendedtoprovideasetofrulesforboarddesignerstofollow,butitisalwaysadvisabletosimulatethefinalimplementationtoensureproperfunctionality.09005aef80cc3dceMicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.TN_47_01.fm-Rev.B12/09EN2©2005MicronTechnology,Inc.Allrightsreserved.TN-47-01DDR2DESIGNGUIDEFORTWO-DIMMSYSTEMSIntroductionFigure1:Two-DIMMUnbufferedDDR2-533MHzTopology1TAddressandCommandBusCLK2,CLK2#CLK3,CLK3#CLK5,CLK5#CLK4,CLK4#VREFCommand/AddressCopy1CLK0,CLK0#CLK1,CLK1#VTTRegulatorDDR2DIMMDQS[63:0],DM[8:0],CB[7:0]ParallelTerminationResistorsDQS[8:0]/DQS#[8:0]Command/AddressCopy2S#[1:0],CKE[1:0],ODT[1:0]S#[3:2],CKE[3:2],ODT[3:2]DDR2MemoryControllerDDR2DIMM09005aef80cc3dceMicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.TN_47_01.fm-Rev.B12/09EN3©2005MicronTechnology,Inc.Allrightsreserved.TN-47-01DDR2DESIGNGUIDEFORTWO-DIMMSYSTEMSIntroductionFigure2:Two-DIMMUnbufferedDDR2-533MHzTopology2TAddressandCommandBusCLK2,CLK2#CLK3,CLK3#CLK5,CLK5#CLK4,CLK4#VREFCommand/AddressCLK0,CLK0#CLK1,CLK1#VTTRegulatorDDR2DIMMDQS[63:0],DM[8:0],CB[7:0]ParallelTerminationResistorsDQS[8:0]/DQS#[8:0]S#[1:0],CKE[1:0],ODT[1:0]S#[3:2],CKE[3:2],ODT[3:2]DDR2MemoryControllerDDR2DIMM09005aef80cc3dceMicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.TN_47_01.fm-Rev.B12/09EN4©2005MicronTechnology,Inc.Allrightsreserved.TN-47-01DDR2DESIGNGUIDEFORTWO-DIMMSYSTEMSDDR2SignalGroupingDDR2SignalGroupingThesignalsthatcomposeaDDR2memorybuscanbedividedintofouruniquegroup-ings,eachwithitsownconfigurationandroutingrules.•DataGroup:DataStrobeDQS[8:0],DataStrobeComplementDQS#[8:0](Optional),DataMaskDM[8:0],DataDQ[63:0],andCheckBitsCB[7:0]�AddressandCommandGroup:BankAddressBA[2:0],AddressA[15:0],andCommandInputsRAS#,CAS#,andWE#.�ControlGroup:ChipSelectS[3:0]#,ClockEnableCKE[3:0],andOn-dieTerminationODT[3:0]�ClockGroup:DifferentialClocksCK[5:0]andCK#[5:0]BoardStackupAtwo-DIMMDDR2channelcanberoutedonafour-layerboard.ThelayoutshouldbedoneusingcontrolledimpedancetracesofZo=50Ω(±10%)characteristicimpedance.AsamplestackupisshowninFigure3.Thetraceimpedanceisbasedona5-mil-widetraceand1/2oz.copperwithadielectricconstantof4.2fortheFR4prepregmaterial.Thisstackupassumesthatthe1/2oz.copperontheouterlayersisplated,foratotalthick-nessof2.1mils.Othersolutionsexistforachivinga50Ωcharacteristicimpedance,soboarddesignersshouldworkwiththeirPCBvendorstospecifyastackup.Figure3:SampleBoardStackup3.5milPrepreg~42milCoreGroundPlane(1oz.cu.)PowerPlane(1oz.cu.)3.5milPrepregSolderSide-SignalLayer