电子设计自动化I随堂练习答案

电子设计自动化I随堂练习答案第6章VHDL结构与要素1.实体下列实体的语句结构是否正确，如果不正确，请指出具体错误。(1)ENTITYmux21ISPORT(a,b:INBIT;s:INBIT;y:OUTBIT);ENDmux21正确(2)ENTITYmux21ISPORT(a,b:INBIT;s:INBIT;y:OUTBIT);ENDENTITY不正确，“END[ENTITY]mux21”(3)entityMUX21isport(A,B:inbit;S:inbit;Y:outbit);endmux21正确(4)ENTITYmux21ISPORT(a,b:INBIT;--a和b分别是数据输入端s:INBIT;y:OUTBIT);ENDENTITYmux21正确(5)ENTITYmcu16ISGENERIC(addrwidth:INTEGER:=16）；PORT(add_bus:OUTSTD_LOGIC_VECTOR(addrwidth-1DOWNTO0));ENDmcu16正确(6)ENTITYmcu8ISGENERIC(addrwidth:INTEGER:=16）；PORT(add_bus:OUTSTD_LOGIC_VECTOR(addrwidth-1DOWNTO0));ENDmcu8正确(7)ENTITYmcu16ISGENERIC(addrwidth:INTEGER）；PORT(add_bus:OUTSTD_LOGIC_VECTOR(addrwidth-1DOWNTO0));ENDmcu16正确(8)ENTITYmcu16ISGENERIC(addrwidth:=16）；PORT(add_bus:OUTSTD_LOGIC_VECTOR(addrwidth-1DOWNTO0));ENDmcu16错误，“GENERIC(addrwidth:INTEGER:=16；“(9)ENTITYmcu16ISGENERIC(addrwidth:INTEGER[:=16]）；PORT(add_bus:OUTSTD_LOGIC_VECTOR(addrwidth-1DOWNTO0));ENDmcu16错误，“GENERIC(addrwidth:INTEGER:=16；“(10)ENTITYnand2ISGENERIC(trise:TIME:=1ns;tfall:TIME:=1ns)；PORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDnand2正确(11)ENTITYgate4ISGENERIC(trise:TIME:=1ns;tfall:TIME:=1ns)；PORT(a:INSTD_LOGIC;c:OUTSTD_LOGIC;d:INOUTSTD_LOGIC;e:BUFFERSTD_LOGIC);ENDgate4正确(12)ENTITYnand2ISGENERIC(trise:TIME:=1ns;tfall:TIME:=1ns)；PORT(a,b:INtrise;c:OUTtfall);ENDnand2错误，trise和tfall不是数据类型(13)ENTITYnand2ISGENERIC(trise:TIME:=1ns;tfall:TIME:=1ns)；ENDnand2错误，实体的语句结构必须包含端口说明2.求下列以数制基数表示的文字的十进制数值16#F.11#E215x162+1x161+1x160=38578#167.2#E11x83+6x82+7x81+2x80=9542#10.0001_1111#E81x29+1x24+1x23+1x22+1x21+1x20=5433.判断下列文字或标识符是否合法“2FFT”合法10#1A#不合法O1A”不合法X#E#E2合法ELSE不合法Not$ack不合法_june不合法june_不合法june__1不合法\AorB\合法/AorB/不合法\A\B\不合法\A/B\合法\Enter\合法“1_1101_1000”合法4.数据类型根据要求定义下列常量（CONSTANT）、变量（VARIABLE）或信号（SIGNAL）TTL高电平5V，TTL低电平0VCONSTANTTTL_H:REAL:=5.0;CONSTANTTTL_L:REAL:=0.0;a大于b结果为真，a小于b结果为假CONSTANTa_gt_b:BOOLEAN:=TRUE;CONSTANTa_lt_b:BOOLEAN:=FALSE;程序编写者xiaomingCONSTANTeditor:STRING:=“xiaoming”;xiaoming的学号201302031111CONSTANTxiaoming_xuehao:STRING:=“201302031111”;xiaoming的EDA考试成绩90分CONSTANTxiaoming_chengji:INTEGER:=90;8位二进制表示的最大十进制数CONSTANT8octect_to_integer:INTEGER:=255;用于LED七段码显示数字“9”CONSTANTnum_9:BIT_VECTOR:=”1111011”;3-8译码器的输入信号SIGNALoct_decoder_input:BIT_VECTOR(2downto0);D触发器输出信号SIGNALD_trigger_output:STD_LOGIC;5.赋值语句根据要求给下列变量（VARIABLE）或信号（SIGNAL）赋值面积a等于a:=3.14*r*r;给8位位矢量的高4位赋值1a(7downto4):=”1111”;给8位位矢量的奇数位赋值1a(7):=”1”;a(5):=”1”;a(3):=”1”;a(1):=”1”;开关量信号初值为低电平SIGNALswitch_signal:BIT:=’0’;EDA考试第一名成绩是99分eda_chengji_1:=99.0;EDA考试第一名的学号是201302031111eda_xuehao_1:=“201302031111”;负反馈电路信号nf给信号y赋值，传输延迟10nsy=nfAFTER10ns;用变量a给信号y赋值y=a;将信号y定义为标准逻辑位类型并设置为未初始化的SIGNALy:STD_LOGIC:=’U’;6.顺序语句(1)根据电路补充VHDL语句abSABZ（a）…SIGNALa,b,z:BIT;PROCESS(a,b)BEGINIF(a=`0`)THENz=a;ELSIF(b=’0’)THENz=a;ELSEz=b;ENDIF;ENDPROCESS;abz（b）…SIGNALa,b,z:BIT;PROCESS(a,b)BEGINIF(a=`1`)THENz=’1’;ELSIF(b=`0`)THENz=’1’;ELSEz=’0’;ENDIF;ENDPROCESS;acbz（c）…SIGNALa,b,c,z:BIT;PROCESS(a,b,c)s=a&b&c;BEGINCASEsISWHEN“111”=z=’1’WHENOTHERS=z=’0’ENDCASE;ENDPROCESS;acbz（d）…SIGNALa,b,c,z:BIT;PROCESS(a,b,c)s=a&b&cBEGINCASEsISWHEN“000”|”011”|”101”|”110”=z=’0’WHENOTHERS=z=’1’ENDCASE;ENDPROCESS;(2)根据功能要求写出语句a)8位比较器SIGNALa,b:BIT_VECTOR(7DOWNTO0);SIGNALa_more_or_equal_to_b:BOOLEAN;…_a_more_or_equal_to_b=FALSE;FORnIN7downto0LOOPIF(a(n)b(n))THENa_more_or_equal_to_b=FALSE;EXIT;ELSIF(a(n)=b(n))THENa_more_or_equal_to_b=TRUE;EXIT;ELSENULL;ENDIF;ENDLOOP;(3)根据语句回答问题a(0to7):=”UUUUUUUU”;b(0to15):=”UUUUUUUUUUUUUUUU”;…L_x:FORnIN0TO7LOOPa(n):=’0’;k:=0;L_y:LOOPb(k):=’0’;NEXTL_xWHEN(k=n);b(k+8):=’0’;k:=k+1;ENDLOOPL_y;ENDLOOPL_x;问上述语句运行结束后变量a和b的值？a(0to7):=”00000000”;b(0to15):=”0000000”;7.并行语句(1)用并行信号赋值语句改造下列顺序语句abSABZ（a）…ARCHITECTUREa_and_not_bOFmux21ISSIGNALa,b,z:BIT;BEGINz=aWHENa=’0’ELSEaWHENb=’0’ELSEb;ENDa_and_not_b;acbz（b）ARCHITECTUREa_xor_b_xor_cOFxor31ISSIGNALa,b,c,z:BIT;BEGINs=a&b&c;WITHsSELECTz=’0’WHEN“000”,’0’WHEN“011”,’0’WHEN“101”,’0’WHEN“110”,’1’WHENOTHERS;ENDa_xor_b_xor_c;(2)补充元件例化部分语句实现电路功能or2_1a1b1c1or2_2a2b2c2or2_4a3b3z2or2_3z1…ENTITYor2ISPORT(a,b:INBIT;c:outBIT);ENDor2;ARCHITECTUREor2behvOFor2ISBEGINc=aorb;ENDor2behv;…ENTITYor62ISPORT(a1,b1,a2,b2,a3,b3:INBIT;z1,z2:outBIT);ENDor62;ARCHITECTUREor62behvOFor62ISCOMPONENTor2PORT(a,b:INBIT;c:outBIT);ENDCOMPONENT;SIGNALc1,c2:BIT;BEGINor2_1:or2PORTMAP(a1,b1,c1);--位置关联方式or2_2:or2PORTMAP(a=a2,b=b2,c=c2);--名字关联方式or2_3:or2PORTMAP(c1,c2,c=z1);--混合关联方式or2_4:or2PORTMAP(a=a3,b=b3,c=z2);ENDor62behv;