sgmii-specification

1of10July19,2001DocumentNumberENG-46158RevisionRevision1.7AuthorYi-ChinChuProjectManagerJRRiversSerial-GMIISpecificationTheSerialGigabitMediaIndependentInterface(SGMII)isdesignedtosatisfythefollowingrequirements:•Conveynetworkdataandportspeedbetweena10/100/1000PHYandaMACwithsignificantlylesssignalpinsthanrequiredforGMII.•Operateinbothhalfandfullduplexandatallportspeeds.ChangeHistoryDefinitionsMII–MediaIndependentInterface:Adigitalinterfacethatprovidesa4-bitwidedatapathbetweena10/100Mbit/sPHYandaMACsublayer.SinceMIIisasubsetofGMII,inthisdocument,wewillusetheterm“GMII”tocoverallofthespecificationregardingtheMIIinterface.GMII–GigabitMediaIndependentInterface:Adigitalinterfacethatprovidesan8-bitwidedatapathbetweena1000Mbit/sPHYandaMACsublayer.Italsosupportsthe4-bitwideMIIRevisionDateDescription1.7July20,20001Clarifydatasamplingandalsothepossiblelossofthefirstbyteofpream-ble.1.6Jan4,20001AddedspecificationsforCiscoSystemsIntellectualProperty.1.5Aug4,2000Specifiedthedatapatternforthebeginningoftheframe(preamble,SFD)fortheframessentfromthePHYtomakethePCSlayerworkproperly.1.4June30,2000TookoutJabberinfo,changedtx_Config_Reg[0]from0to1tomakeAuto-Negotiationwork1.3April17,2000Increasedallowableinputandoutputcommonmoderange.Theoutputhighandlowvoltageswerealsoincreasedappropriately.Addedspecificationforoutputover/undershoot.AddednoteaboutACcouplingandclockrecovery.1.2Feb8,2000AddedtimingbudgetanalysisandreducedLVDSinputthresholdto+/-50mV.1.1Nov10,1999IncoporatedAuto-NegotiationProcessforupdateoflinkstatus1.0Oct.14,1999InitialReleaseSerial-GMIISpecification:ENG-46158Revision1.72of10July19,2001interfaceasdefinedintheIEEE802.3zspecification.Inthisdocument,theterm“GMII”coversall10/100/1000Mbit/sinterfaceoperations.3of10July19,2001OverviewSGMIIusestwodatasignalsandtwoclocksignalstoconveyframedataandlinkrateinformationbetweena10/100/1000PHYandanEthernetMAC.Thedatasignalsoperateat1.25Gbaudandtheclocksoperateat625MHz(aDDRinterface).Duetothespeedofoperation,eachofthesesignalsisrealizedasadifferentialpairthusprovidingsignalintegritywhileminimizingsystemnoise.Figure1illustratesthesimpleconnectionsinasystemutilizingSGMII.Thetransmitandreceivedatapathsleveragethe1000BASE-SXPCSdefinedintheIEEE802.3zspecification(clause36).ThetraditionalGMIIdatasignals(TXD/RXD),datavalidsignals(TX_EN/RX_DV),anderrorsignals(TX_ER/RX_ER)areencoded,serializedandoutputwiththeappropriateDDRclocking.Thusitisa1.25Gbaudinterfacewitha625MHzclock.CarrierSense(CRS)isderived/inferredfromRX_DV,andcollision(COL)islogicallyderivedintheMACwhenRX_DVandTX_ENaresimultaneouslyasserted.Controlinformation,asspecifiedinTable1,istransferredfromthePHYtotheMACtosignalthechangeofthecontrolinformation.ThisisachievedbyusingtheAuto-NegotiationfunctionalitydefinedinClause37oftheIEEESpecification802.3z.Insteadoftheabilityadvertisement,thePHYsendsthecontrolinformationviaitstx_config_Reg[15:0]asspecifiedinTable1wheneverthecontrolinformationchanges.Uponreceivingcontrolinformation,theMACacknowledgestheupdateofthecontrolinformationbyassertingbit14ofitstx_config_reg{15:0]asspecifiedinTable1.SGMIIdetailssourcesynchronousclocking;however,specificimplementationsmaydesiretorecoverclockfromthedataratherthanusethesuppliedclock.Thisoperationisallowed;however,allsourcesofdatamustgeneratetheappropriateclockregardlessofhowtheyclockreceivedata.RXRXCLKTXTXCLKPHYMACCRSCOLRX_CKRX_DVRX_ERRXD[7:0]GTX_CLKTX_CLKTX_ENTX_ER88TXD[7:0]802.3zTransmitPCS802.3zReceivePCS802.3zSynchCOLRX_CLKRX_DVRX_ERRXD[7:0]GTX_CLKTX_CLKTX_ENTX_ERTXD[7:0]CRS8802.3zSynch802.3zTransmitPCS8802.3zReceivePCSFigure1SGMIIConnectivity802.3zAuto-Negotiation802.3zAuto-NegotiationSerial-GMIISpecification:ENG-46158Revision1.74of10July19,2001Thelink_timerinsidetheAuto-Negotiationhasbeenchangedfrom10msecto1.6msectoensureapromptupdateofthelinkstatus.Clearly,SGMII’s1.25Gbaudtransferrateisexcessiveforinterfacesoperatingat10or100Mbps.Whenthesesituationsoccur,theinterface“elongates”theframebyreplicatingeachframebyte10timesfor100Mbpsand100typesfor10Mbps.Thisframeelongationtakesplace“above”the802.3zPCSlayer,thusthestartframedelimiteronlyappearsonceperframe.The802.3zPCSlayermayremovethefirstbyteofthe“elongated”frame.BitNumbertx_config_Reg[15:0]sentfromthePHYtotheMACtx_config_Reg[15:0]sentfromtheMACtothePHY15Link:1=linkup,0=linkdown0:Reservedforfutureuse14ReservedforAuto-Negotiationacknowledgeasspecifiedin802.3z1130:Reservedforfutureuse0:Reservedforfutureuse12Duplexmode:1=fullduplex,0=halfduplex0:Reservedforfutureuse11:10Speed:Bit11,10:11=Reserved10=1000Mbps:1000BASE-TX,1000BASE-X01=100Mbps:100BASE-TX,100BASE-FX00=10Mbps:10BASET,10BASE2,10BASE50:Reservedforfutureuse9:10:Reservedforfutureuse0:Reservedforfutureuse011table1DefinitionofControlInformationpassedbetweenlinksviatx_config_Reg[15:0]5of10July19,2001ImplementationSpecificationThissectiondiscusseshowthisSGMIIinterfaceshallbeimplementedbyincorporatingandmodifyingthePCSlayeroftheIEEESpecification802.3z.SignalMappingatthePHYsideFigure2showsthePHYfunctionalblockdiagram.ItillustrateshowthePCSlayershallbemodifiedandincorporatedatthe