基于FPGA的内存控制器的设计与应用

太原理工大学硕士学位论文基于FPGA的内存控制器的设计与应用姓名：赵冠楠申请学位级别：硕士专业：@指导教师：梁凤梅20100401IFPGASDRSDRAMDDRSDRAMDDR2SDRAMSDRSDRAMDDRSDRAMDDR2SDRAMJEDECSDRSDRAMDDRSDRAMDDR2SDRAMTOP-DOWNVHDLRTLXilinxSpartan3FPGASDRSDRAMDDRSDRAMDDR2SDRAMCMOS()SDRSDRAMDDRSDRAMDDR2SDRAMII()()TOP-DOWNVHDLRTL()ModelsimSynplifyPro()XilinxSpartan3FPGA()CMOSSDR/DDR/DDR2SDRAMSDRSDRAMDDRSDRAMDDR2SDRAMCMOSSDRSDRAMDDRSDRAMDDR2SDRAMFPGAIIIDESIGNANDAPPLICATIONOFMEMORYCONTROLLERBASEDONFPGAABSTRACTCurrently,SDRSDRAM,DDRSDRAMandDDR2SDRAMstilloccupythemainmarketofhigh-speedstoragedevices,andtheyhavebeenwidelyusedinconsumerelectronicproducts,communicationproductsandembeddedsystemsduetogreatadvantages,suchasinexpensiveprice,bigcapacityandhighspeed.ThereforeifamemorycontrollersuitabletoSDRSDRAM,DDRSDRAMandDDR2SDRAMismadetogreatlyfacilitatedesignapplicationdevelopmentandapplicationindifferentsystems,itwillhavegreatutility.BasedonthestudyoftechnicaldocumentaboutSDRSDRAMDDRSDRAandDDR2SDRAMformulatedbyJEDEC,thispaperconcludedasetofinfrastructureforthethreememorycontrollersabovebyanalyzingtheirinternalmodules,operationcommandsandworkflow.ThroughtheTOP-DOWNdesignmethod,italsorealizedlogicaldescriptionsforeachfunctionmoduleinVHDL,andverifiedeachfunctionbysyntheticsimulation.ThenbyusingXilinx’sSpartan3FPGA,hardwareverificationforSDRSDRAMDDRSDRAMandDDR2SDRAMaswellasapplicationresearchinanCMOSimagecapturesystemisachieved.IVThekeypointsinthispapercontainseveralaspectsasfollows:1.ThecrucialtechnologiesofthememorycontrollerssuchasStructureInterfaceandTimingareexplored,andresearchontheKeytechnicalfeaturesinsideSDR,DDRandDDR2controller2.Thestructureofthegeneral-purposememorycontrollerdividedintermsofclockgenerationmodule,controlmodule,commandmodule,instructiondecodingmoduleanddatapathmodule,aswellastheanalysisanddesignforthestructureandimplementationofeachmodule.3.UsingaTOP-DOWNdesignmethodandtheRTLdesignaccomplishmentforeachmoduleinVHDL.4.ThefunctionsimulationbyModelsimaswellasthesynthesizedandlogicaloptimizationunderSynplifyPro.5.ThestructureofahardwaresimulationplatformforeachmemorycontrollerbasedonSpartan-3FPGAofXilinxcorporationandtheaccomplishmentofsimulationverificationformemorycontrollers.6.TheaccomplishmentofapplicationresearchonmemorycontrollerinanCMOSimagecapturesystem.ThisthesisfullydiscussedthedesignprincipleandimplementationofmemorycontrollerssuitabletoSDRSDRAMDDRSDRAMandDDR2SDRAM.MemoryControllersinthispapernotonlyeasytooperate,butalsofavormemorycontrolmainlyreferringtoSDRSDRAM,DDRSDRAMandDDR2SDRAMcontrolwiththecharacteristicsofapplicabilityandVpracticability.Inviewoftheresultfromanimageacquisitionsystem,thestructureofthismemorycontrolleraswellasitsdesigncanbothfulfillthepracticalengineeringrequirement.KEYWORDS:SDRSDRAM,DDRSDRAM,DDR2SDRAM,controller,FPGA1DRAMSDR/DDR/DDR2SDRAM1.11.1.1DRAMCD/VCD/DVDMD[1]RAMROMStaticRAMSRAMDynamicRAMDRAMSRAMCPUCacheCacheDRAMRAMSDRAMSynchronousDynamicRAMSDRAMSDRAMSDRAMSDRSDRAMDDRSDRAMDDR2SDRAMDDR3SDRAM[1]SDRSDRAMSingle-EndedDDRSDRAMDDR2SDRAMDDR32SDRAMSDRSDRAMCLKCLK#CLKCLK#CLKSDR1.1.2SDRSDRAMDDR/DDR2SDRAMSDRSDRAM100MHz5.8nsSDRAMPipelineSDRAMbankbankbankPentium66MHz100MHz133MHzSDRAMPC66PC100PC133PC150PC166DDRSDRAMDualDateRateSDRAMSDRAMDDRDDRSDRAMSDRAMDDRDDRDLLDelayLockedLoop16DDLDDRSDRSDRAMDDR22-bitprefetch212bitcolumnSDRAMDDRSDRAMSDRAMSDRAMDDRDDR2SDRAMDDRSDRAMDDR21.8VDDRSDRAM50DDR243DDR2DDRDDR2CASOCDODTDDR2ODTOnDieTerminationDQSDDR2SDRAMDDR2ODTDDR2ODTDDR2SDRAMFBGADDR2SDRAM1-11.1.3SDRSDRAMDDR/DDR2SDRAMJEDECJointElectronDeviceEngineeringCouncilIntelSDRSDRAMPC100[2]JEDEC2005DDRSDRAMJESD79E[3]2006JEDECDDRSDRAMJESD79-2C[4]41-1SDRAMTable.1-1EvolutionofSDRAMArchitectureSDRSDRAMDDRSDRAMDDR2SDRAMMb/sPC66PC100PC133DDR200,266,333400DDR2-400533667800Banks144/8Pre-fetch1-bit2-bit4-bit124824848MoBoODTDQOCDCAS1231.522.5323453.3V+/-0.3LVTTL2.5V+/-0.2SSTL_21.8V+/-0.1SSTL_18TSOP-II54PinTSOP-II66PinCSP60PinCSPFBGA60/64/68/84/92PinLVTTL=LowVoltageTansistor-TansitorLogic-SSTL=StubSeriesTerminatedLogicJEDECSDRAMSDRAMSDR/DDR/DDR2SDRAM5INTELCorePentiumCeleronMCHMemoryControllerHubNehalemINTELNehalemCorei7DDR3AMDK8CPUCPUAMDOptero128bitsDDRAthlon6464bitsDDRDDRSDRAMDDR2SDRAMDDR3SDRAMQDRRAMBUS1.2SDRSDRAMDDRSDRAMDDR2SDRAM1.JEDECSDR/DDR/DDR2HY57V281620HCTHY5DU56822ATHY5PS12823LFSDR/DDR/DDR22.SDR/DDR/DDR2VHDLRTL3.PCB4.SDRSDRAMDDR/DDR2SDRAMCMOSSDRSDRAMDDRSDRAM6DDR2SDRAM1.3SDRAMSDRSDRAMDDR/DDR2SDRAMSDRSDRAMDDR/DDR2SDRAMVHDLSynplifyProPCBCMOSCMOS7SDR/DDR/DDR2SDRAM2.12.1.1SDRAMsynchronousDynamicRandomAccessMemory1-1RowColumnSDRAM[5]2-1SDRAMFig.2-1SDRAMmemoryarraydiagram1-1BankLogicalBankL-BankL-BankSDRAML-BankColumn123456789101112132-3-4-5-6-7-8-----------9-10-11-12-(Row)ROW8Colunm98SDRAML-BankSDRSDRAM24DDRSDRAM4DDR2SDRAML-Bank48L-BankL-BankL-BankL-Bank.bitbit2-2SDRAM2-2SDRAMFig.2-2SDRAMmemorytheorydiagram2-2DQ2-22-2SenseAmplifierS-AMPI/ODQ0DQ7DQ0DQ792.1.2SDR/DDR/DDR2SDRAMJEDEC[2,3,4]SDR/DDR/DDR2SDRAM()SDRSDRAMSDRSDRAM2-12-1SDRAMTable2-1InterfaceSignalsofSDRAMCLKCKECS#RAS#CAS#WEBA0,BA1BankA0~A11DQ0~DQ15UDQM,LDQMVDD/VSS/VDDQ/VSSQ[2]CLKSDRAMCLKCKESDRSDRAMCS#CLK,CKE,UDQMLDQMRAS#CA