EDA考试题目和答案

设计实验与考核1、设计一个带计数使能、异步复位、带进位输出的增1六位二进制计数器，计数结果由共阴极七段数码管显示。答：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycounterisport(clk,clk1,en,clr:instd_logic;ledout:outstd_logic_vector(6downto0);scanout,scanout1,co:outstd_logic);endcounter;architectureaofcounterissignalcnt:std_logic_vector(7downto0);signalled:std_logic_vector(6downto0);signalscan:std_logic;signalhex:std_logic_vector(3downto0);beginprocess(clk)beginif(clk'eventandclk='1')thenifen='1'thenifclr='1'thencnt=(others='0');elseifcnt=00111111thencnt=00000000;co='1';elsecnt=cnt+'1';co='0';endif;endif;endif;endif;endprocess;process(clk1)beginifclk1'eventandclk1='1'thenscan=notscan;endif;Scanout=scan;Scanout1=notscan;endprocess;ledout=notled;hex=cnt(7downto4)whenscan='1'elsecnt(3downto0);withhexselectled=1111001when0001,0100100when0010,0110000when0011,0011001when0100,0010010when0101,0000010when0110,1111000when0111,0000000when1000,0010000when1001,0001000when1010,0000011when1011,1000110when1100,0100001when1101,0000110when1110,0001110when1111,1000000whenothers;enda;2、设计一个带计数使能、同步复位、带进位输出的增1二十进制计数器，计数结果由共阴极七段数码管显示。答：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycounterisport(clk,clk1,en,clr:instd_logic;co,scanout:outstd_logic;ledout:outstd_logic_vector(6downto0));endcounter;architecturertlofcounterissignalcnt:std_logic_vector(7downto0);signalled:std_logic_vector(6downto0);signalscan:std_logic;signalhex:std_logic_vector(3downto0);beginprocess(clk,clr)beginifclr='1'thencnt=(others='0');elsifclk'eventandclk='1'thenifen='1'thenifcnt=00001001thencnt=00010000;co='0';elsifcnt=00011001then--注意此处，前面跳过了A到F的计数,所以计数到11001cnt=00000000;co='1';elsecnt=cnt+'1';co='0';endif;endif;endif;endprocess;process(clk1)beginifclk1'eventandclk1='1'thenscan=notscan;endif;endprocess;ledout=notled;scanout=scan;hex=cnt(7downto4)whenscan='1'elsecnt(3downto0);withhexselectled=1111001when0001,0100100when0010,0110000when0011,0011001when0100,0010010when0101,0000010when0110,1111000when0111,0000000when1000,0010000when1001,1000000when0000,1111111whenothers;endrtl;3、设计一个带计数使能、异步复位、同步装载的可逆七位二进制计数器，计数结果由共阴极七段数码管显示。答：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycounterisport(clk,clks,clr,en,stdl,dir:instd_logic;din:instd_logic_vector(6downto0);ledout:outstd_logic_vector(6downto0);scanout:outstd_logic);endcounter;architectureaofcounterissignalcnt:std_logic_vector(6downto0);signalhex:std_logic_vector(3downto0);signalled:std_logic_vector(6downto0);signalscan:std_logic;beginprocess(clk)beginif(clk'eventandclk='1')thenifclr='1'thencnt=(others='0');elsifstdl='0'thencnt=din;elsifen='1'thenifdir='1'thencnt=cnt+'1';elsecnt=cnt-'1';endif;endif;endif;endprocess;process(clks)beginif(clks'eventandclks='1')thenscan=notscan;endif;endprocess;scanout=scan;ledout=notled;hex='0'&cnt(6downto4)whenscan='1'elsecnt(3downto0);withhexselectled=1111001when0001,0100100when0010,0110000when0011,0011001when0100,0010010when0101,0000010when0110,1111000when0111,0000000when1000,0010000when1001,0001000when1010,0000011when1011,1000110when1100,0100001when1101,0000110when1110,0001110when1111,1000000whenothers;enda;4、设计一个带计数使能、同步复位、异步装载、可逆计数的通用计数器。计数结果由共阴极七段数码管显示。答：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYcounterISGENERIC(count_value:INTEGER:=9);PORT(clk,clr,en,load,dir:INSTD_LOGIC;data_in:ININTEGERRANGE0TOcount_value;ledout:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDcounter;ARCHITECTUREaOFcounterISSIGNALcnt:INTEGERRANGE0TOcount_value;SIGNALled:STD_LOGIC_VECTOR(6DOWNTO0);BEGINPROCESS(load,clk)BEGINIFload='1'THENcnt=data_in;elsifclr='1'THENcnt=0;ELSIF(clk'EVENTANDclk='1')THENIFen='1'THENIFdir='1'THENIFcnt=count_valueTHENcnt=0;ELSEcnt=cnt+1;endif;elseIFcnt=0THENcnt=count_value;elsecnt=cnt-1;endif;endif;endif;endif;ENDPROCESS;ledout=NOTled;WITHcntSELECTled=1111001WHEN1,0100100WHEN2,0110000WHEN3,0011001WHEN4,0010010WHEN5,0000010WHEN6,1111000WHEN7,0000000WHEN8,0010000WHEN9,1000000WHEN0,1111111WHENothers;ENDa;5、设计一个具有16分频、8分频、4分频和2分频功能的多用分频器。答：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYdiv4ISPORT(clk:INSTD_LOGIC;din:INSTD_LOGIC_VECTOR(3DOWNTO0);fout:OUTstd_LOGIC);ENDdiv4;ARCHITECTUREaOFdiv4ISbeginprocess(clk)variablecnt:std_logic_vector(3downto0);beginif(clk'eventandclk='1')thenifcnt=1111thencnt:=0000;elsecnt:=cnt+'1';endif;ifdin=0000thenfout=cnt(3);elsifdin=1000thenfout=cnt(2);elsifdin=1100thenfout=cnt(1);elsifdin=1110thenfout=cnt(0);elsefout='1';endif;endif;endprocess;enda;6、设计一个正负脉宽相等的通用分频器。答：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYdivISGENERIC(num:INTEGER:=2);PORT(clk:INSTD_LOGIC;co:OUTSTD_LOGIC);ENDdiv;ARCHITECTURErtlOFdivISBEGINPROCESS(clk)VARIABLEcnt:STD_LOGIC_VECTOR(numdownto0);BEGINIF(clk'eventandclk='1')THENcnt:=cnt+'1';ENDIF;co=cnt(num);ENDPROCESS;ENDrtl;7、根据需要设计一个多用分频器：可以控制实现四种分频形式：第一种：5分频第二种：8分频第三种：15分频第四种：16分频答：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityfenpinisport(clk:instd_log