Verilog--2001

July2002Verilog2001FeatureUpdateVerilog2001officiallyknownasIEEEStd.1364-2001isthelatestupdatetotheVerilogHardwareDescriptionLanguageandtheVerilogProgrammingLanguageInterface.Thisstandardaddsseveralfeaturestothepreviousstandardofthelanguage,theIEEEStd.1364-1995alsocalledVerilog1995.ThisapplicationnotehighlightsthefeaturessupportedinSynplify®andSynplifyPro®softwareversion7.1.ItalsoaddresseshowtosettheSynplifyandSynplifyProsoftwaretoaccepttheVerilog2001constructs.ThekeyfeaturesofVerilog2001are:•Verilog1995andVerilog2001PortandDataTypeDeclarationsVerilog2001CombinesPortandDataTypeDeclarationsMinimizingVerbositySensitivityListSignedArithmeticSupportParameterSupportPowerOperatorGenerateStatementsVerilog1995andVerilog2001PortandDataTypeDeclarationsVerilog1995requiresbothportanddatatypedeclarationstodefineaport.Theportanddatatypedeclarationscover:directionoftheporttypeoftheportwidthoftheportVerilog1995PortDefinitionThefollowingVerilog1995portdefinitionexampledescribestheportsofan8-bitaddermoduledefinedbytwotypesofdeclarations:firstaportdeclarationdescribestheportdirectionandthenthedatatypedeclarationdescribestheporttype(wire)andwidth.moduleadder_8(a,b,cin,sum,cout);input[7:0]a,b;inputcin;output[7:0]sum;outputcout;Page2Synplicity,Inc.ApplicationNotereg[7:0]sum;wire[7:0]a,b;wirecin;regcout;Asshownintheportsumexampleusingthe1995Verilogstandard,theportsummustbedefinedintwodistinctstatements:oneshowingtheportwidthanddirectiontheothershowingtheportdatatypeVerilog2001PortDefinitionVerilog2001introducesalessverboseportdefinitionbycombiningseparateportanddatatypedeclarationsintoonedeclaration.UsingtheVerilog2001standard,thepreviousexamplecanbewrittenas:moduleadder_8(a,b,cin,sum,cout);inputwire[7:0]a,b;inputwirecin;outputreg[7:0]sum;outputregcout;Note:BoththeVerilog1995andtheVerilog2001standardscanbeusedinthesamedesign.AlthoughVerilog2001isbackwardcompatible,usingonlyonestandardperfileisrecommendedtoeliminatepossiblemisinterpretationofelementswhenbothVerilog1995andverilog2001areusedinthesamefile.Verilog2001CombinesPortandDataTypeDeclarationsMinimizingVerbosityPortdeclarationinVerilog1995requires:portsofthemodulemustbelistedinparenthesis.portinformation(width,direction,anddatatype)mustbedeclaredwithinthemod-ule.Forthepreceding“Verilog1995PortDefinition”example,theportsumwaslistedthreetimes,onceintheportlist,onceintheportdeclaration,andonceinthedatatypedeclaration.InVerilog2001youcancombinethesedeclarationsoftheportlistandminimizeverbosityasshowninthefollowingupdatedexampleofthe8-bitaddermoduleportlistinwhichtheportlistandtheportsumhavebeencombined:moduleadder_8(input[7:0]a,input[7:0]b,inputcin,outputsum,outputcout);Synplicity,Inc.ApplicationNotePage3Verilog2001alsoletsyoucombinetheportdeclarationandthedatatypeoftheporttosupportthefulldeclarationoftheportwithintheportlist.Therefore,theaboveexamplecanbewrittenmoresuccinctlyas:moduleadder_8(inputwire[7:0]a,inputwire[7:0]b,inputwirecin,outputreg[7:0]sum,outputregcout);UsingtheTaskFunction,CombinePortList,TypeInformation,andTaskBycombiningtheportlistandtypeinformation,theabovefeaturesareapplicabletofunctionsandtasksasthetaskbelowillustrates:taskparity_check;input[15:0]data_in;outputeven;outputodd;wire[15,10]dat_inwireeven,odd;…endtaskVerilog2001CombinedFunctionsPortList,DataInformation,DataType,andTaskCombiningallaspectsofportlist,datainformation,datatype,andtask,theVerilog2001standardforthisexamplecanbewrittenmostsuccinctlyasshownbelow.taskparity_check(inputwire[15:0]data_in,outputwireeven,outputwireodd);SensitivityListThissectiondescribesthedifferencesinusingacommaandcombinationallogicconstructswhenusedinVerilog1995andVerilog2001sensitivitylists.CommaSeparatedSensitivityListInVerilog1995,multiplesignalsinthesensitivitylistareseparatedwiththeorkeywordasshowintheexamplebelow.always@(negedgerstorposedgeclk)if(!reset)q=0;Elseq=d;InVerilog2001,youcanuseacommatoseparatethesignalsinthesensitivitylist.Thepreviousexamplescanbewrittenas:always@(negedgerst,posedgeclk)Page4Synplicity,Inc.ApplicationNoteCombinationalLogicSensitivityList:@*and@(*)ConstructsTocorrectlymodelcombinationallogic,allsignalsusedintherighthandsideoftheexpressionmustbelistedinthesensitivitylistasshowninthefollowingexample:always@(a,b,cin)sum=a+b+cin;Note:Whenatleastoneoftheelementsinthesensitivitylistisspecified,theSynplicity®synthesistoolassumescompletenessofthesensitivitylistforcombinationallogic.However,thesimulatorwillnotcompleteanincompletesensitivitylistanditwillerrorout.Forexample,intheaboveexample,ifyouhadnotincludedoneoftheelementsinthesensitivitylistontherighthandsideoftheexpression,theSynplifysynthesistoolwouldhaveincludedwhicheverelementyouhadleftoutofthelist.However,thesimulatorwouldnothaveassumedthemissingelementwasthere,ifyouhadnotexplicitlyspecifieditaspartoftheexpression.InVerilog2001,twonewfeatureshavebeenadded,@*and@(*)whichrepresentallthesignalswhicharereadbythefollowingstatementorstatementgrouprepresentedwithinthebegin-endstatements.Thetwosymbols@(*)and@*areequivalentandinterchang