实验报告模板

同济大学计算机科学与技术系计算机组成原理课程实验报告学号1452312姓名冯凯专业计算机科学与技术授课老师王力生日期2016.06.18一、实验目标1、熟悉Verilog语言的编写。2、掌握计算机的每个部件的构成逻辑及工作原理，计算机各部件之间的连接逻辑，计算机整机的工作原理。3、掌握CPU功能。4、设计55条单周期指令CPU下板成功2、.在自己的CPU上跑一个汇编程序二、总体设计1.作品功能设计及原理说明modulecomp(inputclock,inputresetn,output[2:0]r,output[2:0]g,output[1:0]b,outpuths,outputvs,);2.硬件逻辑图三、主要模块设计1.ALUmodulealu(input[31:0]a,input[31:0]b,input[3:0]aluc,output[31:0]r,outputzero,//零标志outputcarry,//进位标志位outputnegative,//负数标志位outputoverflow//溢出标志位);wire[31:0]d_and=a&b;//0100wire[31:0]d_or=a|b;//0101wire[31:0]d_xor=a^b;//0110wire[31:0]d_nor=~(a|b);//0111wire[31:0]d_lui={b[15:0],16'h0};//100xwire[31:0]d_slt=ab?1:0;wire[31:0]d_sltu=(a[31]&&~b[31])||(a[31]&&b[31]&&ab)||(~a[31]&&~b[31]&&ab);wire[31:0]d_and_or=aluc[0]?d_or:d_and;wire[31:0]d_xor_nor=aluc[0]?d_nor:d_xor;wire[31:0]d_and_or_xor_nor=aluc[1]?d_xor_nor:d_and_or;wire[31:0]d_slt_sltu=aluc[0]?d_slt:d_sltu;wire[31:0]d_lui_slt_sltu=aluc[1]?d_slt_sltu:d_lui;wire[31:0]d_as;wire[31:0]d_sh;wirecarry_as;wirenegative_as;wireoverflow_as;wirecarry_sh;addsub32as32(a,b,aluc[0],aluc[1],d_as,carry_as,overflow_as);shiftshifter(b,a[4:0],~aluc[1],~aluc[0],d_sh,carry_sh);mux4x32select_d(d_as,d_and_or_xor_nor,d_lui_slt_sltu,d_sh,aluc[3:2],r);mux4x1select_carry(carry_as,1'b0,1'b0,carry_sh,aluc[3:2],carry);mux4x1select_overflow(overflow_as,1'b0,1'b0,overflow_sh,aluc[3:2],overflow);assignzero=~|r;assignnegative=r[31];endmodule2.regfilemoduleregfile(input[4:0]raddr1,input[4:0]raddr2,input[31:0]wdata,input[4:0]waddr,inputwe,inputclk,inputrst,output[31:0]radata1,output[31:0]radata2);reg[31:0]register[0:31];assignradata1=(raddr1==0)?0:register[raddr1];assignradata2=(raddr2==0)?0:register[raddr2];integeri;always@(posedgerstornegedgeclk)beginif(rst==1)beginfor(i=1;i32;i=i+1)beginregister[i]=0;endendelsebeginregister[0]=32'b0;if((waddr!=0)&&we)beginregister[waddr]=wdata;endendendendmodule3.CP0moduleCoprocessor0(inputclk,input[4:0]C0adr,input[31:0]C0Wdata,inputC0Write,input[31:0]InteCause,inputInterrupt,outputInteAccept,output[31:0]C0State,outputreg[31:0]C0Data);parameterEPCadr=5'h0;parameterCauseadr=5'h1;parameterStateadr=5'h2;reg[31:0]EPC;reg[31:0]Cause;reg[31:0]State;initialbeginState=32'h1;Cause=32'h0;EPC=32'h0;endassignC0State=State;assignInteAccept=(C0Write&&(C0adr==Stateadr))&&Interrupt&&~C0Wdata[1]||~(C0Write&&(C0adr==Stateadr))&&~(C0Write&&(C0adr==Causeadr))&&Interrupt&&~State[1];always@(posedgeclk)beginif(C0Write)beginif(C0adr==EPCadr)beginEPC=C0Wdata;if(Interrupt&&~State[1])beginState=State|32'b10;Cause=InteCause;endendif(C0adr==Stateadr)beginif(Interrupt&&~C0Wdata[1])beginState=C0Wdata|32'b10;Cause=InteCause;endelsebeginState=C0Wdata;endendif(C0adr==Causeadr)beginCause=C0Wdata;endendelsebeginif(Interrupt&&~State[1])beginState=State|32'b10;Cause=InteCause;endendcase(C0adr)EPCadr:beginC0Data=EPC;endCauseadr:beginC0Data=Cause;endStateadr:beginC0Data=State;endendcaseendendmodule4.pc_regmodulepc_reg(inputclk,inputrst,input[31:0]data_in,outputreg[31:0]data_out);always@(posedgeclk)beginif(rst==1)begindata_out=0;endelsebegindata_out=data_in;endendendmodule5.mulmodulemul(input[31:0]a,input[31:0]b,inputwe,inputu,//1有符号，0无符号output[31:0]hi,output[31:0]lo);reg[32:0]a_bi[32:0];integeri;integerj;wire[32:0]ai;wire[32:0]bi;wire[65:0]z;assignai=u?{a[31],a}:{1'b0,a};assignbi=u?{b[31],b}:{1'b0,b};always@(*)beginif(we)for(i=0;i32;i=i+1)for(j=0;j32;j=j+1)a_bi[i][j]=ai[i]&bi[j];for(i=0;i32;i=i+1)a_bi[i][32]=~(ai[i]&bi[32]);for(j=0;j32;j=j+1)a_bi[32][j]=~(ai[32]&bi[j]);a_bi[32][32]=ai[32]&bi[32];endassignz={33'b1,a_bi[0][32],a_bi[0][31:0]}+(((({32'b0,a_bi[1][32],a_bi[1][31:0],1'b0}+{31'b0,a_bi[2][32],a_bi[2][31:0],2'b0})+({30'b0,a_bi[3][32],a_bi[3][31:0],3'b0}+{29'b0,a_bi[4][32],a_bi[4][31:0],4'b0}))+(({28'b0,a_bi[5][32],a_bi[5][31:0],5'b0}+{27'b0,a_bi[6][32],a_bi[6][31:0],6'b0})+({26'b0,a_bi[7][32],a_bi[7][31:0],7'b0}+{25'b0,a_bi[8][32],a_bi[8][31:0],8'b0})))+((({24'b0,a_bi[9][32],a_bi[9][31:0],9'b0}+{23'b0,a_bi[10][32],a_bi[10][31:0],10'b0})+({22'b0,a_bi[11][32],a_bi[11][31:0],11'b0}+{21'b0,a_bi[12][32],a_bi[12][31:0],12'b0}))+(({20'b0,a_bi[13][32],a_bi[13][31:0],13'b0}+{19'b0,a_bi[14][32],a_bi[14][31:0],14'b0})+({18'b0,a_bi[15][32],a_bi[15][31:0],15'b0}+{17'b0,a_bi[16][32],a_bi[16][31:0],16'b0}))))+(((({16'b0,a_bi[17][32],a_bi[17][31:0],17'b0}+{15'b0,a_bi[18][32],a_bi[18][31:0],18'b0})+({14'b0,a_bi[19][32],a_bi[19][31:0],19'b0}+{13'b0,a_bi[20][32],a_bi[20][31:0],20'b0}))+(({12'b0,a_bi[21][32],a_bi[21][31:0],21'b0}+{11'b0,a_bi[22][32],a_bi[22][31:0],22'b0})+({10'b0,a_bi[23][32],a_bi[23][31:0],23'b0}+{9'b0,a_bi[24][32],a_bi[24][31:0],24'b0})))+((({8'b0,a_bi[25][32],a_bi[25][31:0],25'b0}+{7'b0,a_bi[26][32],a_bi[26][31:0],26'b0})+({6'b0,a_bi[27][32],a_bi[27][31:0],27'b0}+{5'b0,a_bi[28][32],a_bi[28][31:0],28'b0}))+(({4'b0,a_bi[29][32],a_bi[29][31:0],29'b0}+{3'b0,a_bi[30][32],a_bi[30][31:0],30'b0})+({2'b0,a_bi[31][32],a_bi[31][31:0],31'b0}+{1'b1,a_bi[32][32],a_bi[32][31:0],32'b0}))));assignhi=z[63:32];assignlo=z[31:0];endmodule6.divmodulediv(input[31:0]a1,//被除数低位