VHDL设计一个24进制BCD码计数器。

：设计一个24进制BCD码计数器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYh24ISPORT(CLK1HZ:INSTD_LOGIC;EN:INSTD_LOGIC;LOW:OUTSTD_LOGIC_VECTOR(3DOWNTO0);HIGH:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDh24;ARCHITECTURErtlofh24ISSIGNALLOW_REG:STD_LOGIC_VECTOR(3DOWNTO0):=0000;SIGNALHIGH_REG:STD_LOGIC_VECTOR(3DOWNTO0):=0000;SIGNALCLR:STD_LOGIC:='0';BEGIN--个位计数LOW_PROC:PROCESS(CLK1HZ,EN,CLR)BEGINIFrising_edge(CLK1HZ)THENIFEN='1'THENIFLOW_REG=1001ORCLR='1'THEN--23：59进位LOW_REG=0000;ELSELOW_REG=LOW_REG+'1';ENDIF;ENDIF;ENDIF;ENDPROCESS;LOW=LOW_REG;--十位计数HIGH_PROC:PROCESS(CLK1HZ,EN,CLR)BEGINIFrising_edge(CLK1HZ)THENIFEN='1'THENIFCLR='1'THENHIGH_REG=0000;ELSIFLOW_REG=1001THENHIGH_REG=HIGH_REG+'1';ENDIF;ENDIF;ENDIF;ENDPROCESS;HIGH=HIGH_REG;CLR='1'WHENLOW_REG=0011ANDHIGH_REG=0010ELSE'0';--23点以后进位ENDrtl;