VCS-VERDI仿真脚本

VCS编译脚本：将以下代码保存为**.sh（shell脚本）即可#!/bin/csh-f##############################################################setTEST_TOP_NAME=test_spi_interface.vsetRTL_TOP_NAME=spi_interface.v#includesearchpathformodulessetINC_DIRS=+incdir+/home/project/project2018/digital_ic/AI4018/RTL/source#librarysearchpathformodulessetLIB_DIRS=-y/home/project/project2018/digital_ic/AI4018/RTL/lib#toprtlverilogfilesetRTL_TOP_FILE=/home/project/project2018/digital_ic/AI4018/RTL/source/$RTL_TOP_NAME#setSEG_CTRL_FILE=../code/rtl/disp/sdh_seg_ctrl.v#testtopverilogfilesetTEST_TOP_FILE=/home/project/project2018/digital_ic/AI4018/RTL/simulation/$TEST_TOP_NAMEechosimulationtopfile=$TEST_TOP_FILEechoRTLtopfile=$RTL_TOP_FILE#definevcscompileflagssetVCS_FLAGS=\-sverilog\-debug_all\-timescale=1ns/10ps\+libext+.v\-P$LD_LIBRARY_PATH/novas.tab$LD_LIBRARY_PATH/pli.a\-notice-lvcs_information.log\+nospecify\+notimingcheck\+lint=TFIPC-L\+define+FSDB#definecodecoveragemetricssetCM_COMPILE_FLAGS=\-cmline+cond+fsm+tgl\-cm_tglmda#setcoveragetestsetCM_SIM_FLAGS=\-cmline+tgl+fsm+cond#excuteVCSsimatmy_vcsdirectorycd/home/project/project2018/digital_ic/AI4018/VCS/my_vcs#compileusingtheHDLsimulatortoproduceanexecutablevcs$VCS_FLAGS$INC_DIRS$LIB_DIRS$CM_COMPILE_FLAGS$RTL_TOP_FILE$TEST_TOP_FILE#./simv-ucli$CM_SIM_FLAGS-i../script/vcs_ucli.tcl#./simv-gui./simv-ucli-i../script/vcs_ucli.tcl#DVEGUIconverageanalysis#dve-cov-dirsimv.vdb#genaratehtmlconverageanalysisresults#urg-dirsimv.vdb-reportboth-full64Verdi波形仿真脚本：将以下代码保存为**.tcl（tcl脚本）即可#!/bin/csh-f#excuteVCSsimatmy_vcsdirectorycd/home/project/project2018/digital_ic/AI4018/VCS/my_vcs#setverditopandFSDBsetVERDI_TOP=test_spi_interfacesetMY_FSDB=test_spi_interfaceverdi-sv-f../script/verilog_file_list.f\-top$VERDI_TOP\-nologo\-ssf./my_fsdb/$MY_FSDB.fsdb&