FPGA高级时序综合教程

©2003Xilinx,Inc.AllRightsReservedAdvancedTimingConstrainXilinxGSDAsiaPacificAdvancedTimingConstrain-5-3©2003Xilinx,Inc.AllRightsReservedAgenda•Constraints–•–AdvancedTimingConstrain-5-4©2003Xilinx,Inc.AllRightsReservedOverview•••••AdvancedTimingConstrain-5-5©2003Xilinx,Inc.AllRightsReservedTheUCFFile•UCF=UserConstraintsFile•XilinxConstraintsEditorGUI–•XilinxPERIOD,HIGH,LOW,ns,ps,•“;”•“”•AdvancedTimingConstrain-5-6©2003Xilinx,Inc.AllRightsReservedReviewofConstraintFlowPHYSICALDOMAINLOGICALDOMAINDESIGNTRANSLATIONTRCEFPGAEditorXNF/EDIFnetlistUCFUserConstraintsFileNGDBUILDMAPPARNCFSynthesisConstraintsFilePCFPhysicalConstraintsFileAdvancedTimingConstrain-5-7©2003Xilinx,Inc.AllRightsReservedOverview•••••AdvancedTimingConstrain-5-8©2003Xilinx,Inc.AllRightsReservedTimingConstrainDQLogicCircuitryLogicCircuitryLogicCircuitryDQLogicCircuitryLogicCircuitryLogicCircuitryDQDQFPGAclockIPADIPADIPADOPADOPADOffsetInPeriodOffsetOutFrom:ToAdvancedTimingConstrain-5-9©2003Xilinx,Inc.AllRightsReservedOverview•–PERIOD•–OFFSETIN–OFFSETOUT•FROM:TO–PADPAD–AdvancedTimingConstrain-5-10©2003Xilinx,Inc.AllRightsReservedPeriodEstimationPeriodTclk=Tcko+Tnet1+Tlogic+Tnet2Tclk_skewTclk_skew=Tcd2Tcd1DQFLOP0QFLOP0DTckoTnet2Tset_upTlogicTcd1Tcd2Tnet1AdvancedTimingConstrain-5-11©2003Xilinx,Inc.AllRightsReservedEnteringPeriodConstraintClocksinthedesignEnterperiodconstraintDoubleclicktoseemoreoptionsCreatethegroupwithTNM_NET,thenconstrainthegroupwithaPERIODconstraintAdvancedTimingConstrain-5-12©2003Xilinx,Inc.AllRightsReservedQff_0fDQff_90DDCMCLKINCLK0CLK90clk20gclk20_90gclk20Tiopi=0.825net=0.798Tdcmino=-4.197net=0.852net=0.860net=0.639Tgi0o=0.860net=0.639TRCEclockskew–(0.825+0.798+-4.197+0.860+0.860+0.639)-(0.825+0.798+-4.197+0.852+0.860+0.639)=.008nsAdvancedTimingConstrain-5-13©2003Xilinx,Inc.AllRightsReservedBasicPeriodReportSlackequationLogicLevelsOnlylevelsoflogic,notClocktoOutandSetupUpdated!Clocknamesandtimeofactiveedge.IncludesClockPhaseWeblinktographicalpictureofdelaytype!(InTimingAnalyzer)DatapathwithCrossProbingLinkstoFloorplannerorSynthesisTool(InTimingAnalyzer)BasicelementtypeislistedAdvancedTimingConstrain-5-14©2003Xilinx,Inc.AllRightsReservedDCMCLKINCLK0CLK90clk20clk20_0clk20_90PeriodConstraintwithDCM•DCMNETclk20TNM_NET=clk20;TIMESPECTS_clk20=PERIODclk2020nsHIGH50%;•TranslateDCMCLK0:TS_clk20_0=PERIODclk20_0TS_clk20*1.000000HIGH50.000000%CLK90:TS_clk20_90=PERIODclk20_90TS_clk20*1.000000PHASE+5.000000nSHIGH50.000000%AdvancedTimingConstrain-5-15©2003Xilinx,Inc.AllRightsReservedClockPhasePeriodExampleNew!CLK0CLK900102030405152535Qff_0fDQff_90DDCMCLKINCLK0CLK90clk20gclk20_90g15nsAdvancedTimingConstrain-5-16©2003Xilinx,Inc.AllRightsReservedHoldCalculations•holdviolation–ClockSkewAdvancedTimingConstrain-5-17©2003Xilinx,Inc.AllRightsReservedHoldCalculationsCLK(atsourceFF)024681012DATA(atsourceoutputFF)CLK(atdestinationFF)DATA(atdestinationinputFF)QSourceDQDestinationDCLKDATA2ns1nsDATA_IN(atsourceinputFF)DATA_OUT(atdestinationoutputFF)DATA1DATA0DATA1DATA0DATA1DATA0DATA1DATA2DATA_INDATA_OUTAdvancedTimingConstrain-5-18©2003Xilinx,Inc.AllRightsReservedConstraintsOverview•–PERIOD•–OFFSETIN–OFFSETOUT•FROM:TO–PADPAD–AdvancedTimingConstrain-5-19©2003Xilinx,Inc.AllRightsReservedOFFSETConstraint•FPGAPAD•PERIODHIGH/LOW–()•TIMESPECTS_clock=PERIODclock10nsHIGH50%;–•TIMESPECTS_clock=PERIODclock10nsLOW50%;•OFFSET:–OFFSET=INdelaynsBEFOREclk_group;–OFFSET=OUTdelaynsAFTERclk_group;AdvancedTimingConstrain-5-20©2003Xilinx,Inc.AllRightsReservedOFFSETINConstraint•PAD.•=ConstrainedDataPathBUFGCLKAADATAOUT2OUT1QFLOP3DQFLOP1DQFLOP5DQFLOP4DBUS[7..0]CDATAQFLOP2DBUFGCLKB=UnconstrainedDataPathAdvancedTimingConstrain-5-21©2003Xilinx,Inc.AllRightsReservedOFFSETINAFTERConstraint•–Tarrival=Tcko+Toutput+Tlogic–NETData_InOFFSET=INTarrivalAFTERCLK•TinputTarrival+Tinput+TsetupTclkDQQDTckoTinputTset_upTlogicToutputClkFPGAAdvancedTimingConstrain-5-22©2003Xilinx,Inc.AllRightsReservedOFFSETINBEFOREConstraintTarrivalTdelay_maxTperiod•OFFSET_IN_BEFOREOFFSET_IN_AFTER•–NETData_InOFFSET=INTdelayBEFORECLK–Tdelay–TdelayTperiod-TarrivalAdvancedTimingConstrain-5-23©2003Xilinx,Inc.AllRightsReservedEnteringGlobalOFFSETINConstraintClocksinthedesignEntersetuptimeGeneratedUCFconstraintsAdvancedTimingConstrain-5-24©2003Xilinx,Inc.AllRightsReservedEnteringSpecificOFFSETINConstraintPortsinthedesign,DoubleclicktochangeorderofPortsDoubleclocktoentersetuptimeGeneratedUCFconstraintsPortsTabtodefineportspecifictimingCreategroupsinsteadofcreatingconstraintforeachnetAdvancedTimingConstrain-5-25©2003Xilinx,Inc.AllRightsReservedOFFSETINReportExampleSlackequationDataPathDelayClockPathDelayClocknameandtimeofactiveedgeAdvancedTimingConstrain-5-26©2003Xilinx,Inc.AllRightsReservedOFFSETOUTConstraint•PAD•=ConstrainedDataPathBUFGCLKAADATAOUT2OUT1QFLOP3DQFLOP1DQFLOP5DQFLOP4DBUS[7..0]CDATAQFLOP2DBUFGCLKB=UnconstrainedDataPathAdvancedTimingConstrain-5-27©2003Xilinx,Inc.AllRightsReservedOFFSETOUTBEFOREConstraint•–Tstable=Tlogic+Tinput+Tsetup–NETData_OutOFFSET=OUTTstableBEFORECLK•Tcko+Toutput+TstableTclkDQQD