四位全加器的VHDL设计

一位全加器真值表一位全加器的逻辑表达式•S=A⊕B⊕Cin•Co=AB+BCin+ACin•其中A,B为要相加的数，Cin为进位输•入；S为和，Co是进位输出；Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntityfulladderIsPort(Ci,a,b:INstd_logic;s,Co:OUTstd_logic);Endfulladder;Architecturem1OffulladderIsSignaltmp:std_logic_vector(1downto0);Begintmp=('0'&a)+b+Ci;s=tmp(0);Co=tmp(1);Endm1;一位全加器的数据流（逻辑）描述•Libraryieee;•Useieee.std_logic_1164.all;•Useieee.std_logic_unsigned.all;•Entityfulladderis•Port(A,B,CI:instd_logic;•S,CO:outstd_logic);•Endfulladder;•Architecturedataflowoffulladderis•Begin•S=CIxorAxorB;•CO=(AandB)or(CIandA)or(CIandB);•Enddataflow;一位全加器的行为描述•Libraryieee;•Useieee.std_logic_1164.all;•Useieee.std_logic_unsigned.all;•Entityfulladderis•Port(a,b,cin:Inbit;•sum,cout:Outbit);•Endfulladder;•ArchitecturebehaveOffulladderIs•Begin•Process(a,b,cin)•Begin•If(aOrbOrcin)=‘0’Then•sum=‘0’;•cout=‘0’;•Elsif(aANDbANDcin)=’1’Then•sum=‘1’;•cout=‘1’;•Elsif(aXORbXORcin)=’0’Then•sum=‘0’;•cout=‘1’;•Else•sum=‘1’;•cout=‘0’;•EndIf;•EndProcess;•Endbehave;4位全加器的设计，先设计4个1位的全加器，然后将低位的进位输出与高位的进位输入相连，将要进行加法运算的两个4位数的每一位分别作为每一个1位全加器的输入，进行加法运算，所有的1位全加器的输出组成一个4位数，即输入的两个4位数之和，最高位的全加器产生的进位输出即两个4位数求和的进位输出。（如图）Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Entityadder4IsPort(Cin:INstd_logic;x,y:INstd_logic_vector(3downto0);sum:OUTstd_logic_vector(3downto0);Cout:OUTstd_logic);Endadder4;ArchitectureaxOfadder4IsSignalc:std_logic_vector(0to4);ComponentfulladderPort(Ci,a,b:INstd_logic;s,Co:OUTstd_logic);Endcomponent;Beginc(0)=Cin;U1:fulladderPortMap(c(0),x(0),y(0),sum(0),c(1));--U1:fulladderPortMap(Ci=c(0),a=x(0),b=y(0),s=sum(0),Co=c(1));U2:fulladderPortMap(c(1),x(1),y(1),sum(1),c(2));U3:fulladderPortMap(c(2),x(2),y(2),sum(2),c(3));U4:fulladderPortMap(c(3),x(3),y(3),sum(3),c(4));Cout=c(4);Endax;•libraryieee;•useieee.std_logic_1164.all;•useieee.std_logic_unsigned.all;•entityadder4bitis•port(cin:instd_logic;•a,b:instd_logic_vector(3downto0);•s:outstd_logic_vector(3downto0);•cout:outstd_logic);•endadder4bit;•architecturebehofadder4bitis•signalsint:std_logic_vector(4downto0);•signalaa,bb:std_logic_vector(4downto0);•begin•aa='0'&a(3downto0);•bb='0'&b(3downto0);•sint=aa+bb+cin;•s(3downto0)=sint(3downto0);•cout=sint(4);•endbeh;