MC9S12D-DataSheet

©MOTOROLA2002Thisdocumentcontainsinformationonanewproduct.Specificationsandinformationhereinaresubjecttochangewithoutnotice.MOTOROLASEMICONDUCTORTECHNICALDATAMC9S12D-FamilyPPRev6.1,23-Oct-02MC9S12D-FamilyProductBrief16-BitMicrocontrollerDesignedforautomotivemultiplexingapplications,membersoftheMC9S12D-Familyof16bitFlash-basedmicrocontrollersarefullypincompatibleandenableuserstochoosebetweendifferentmemoryandperipheraloptionsforscalabledesigns.AllMC9S12D-Familymembersarecomposedofstandardon-chipperipheralsincludinga16-bitcentralprocessingunit(CPU12),upto512KbytesofFlashEEPROM,14KbytesofRAM,4KbytesofEEPROM,twoasynchronousserialcommunicationsinterfaces(SCI),threeserialperipheralinterfaces(SPI),IIC-bus,anenhancedcapturetimer(ECT),two8-channel10-bitanalog-to-digitalconverters(ADC),aneight-channelpulse-widthmodulator(PWM),J1850interfaceanduptofiveCAN2.0A,Bsoftwarecompatiblemodules(MSCAN12).Systemresourcemapping,clockgeneration,interruptcontrolandbusinterfacingaremanagedbythesystemintegrationmodule(SIM).TheMC9S12D-Familyhasfull16-bitdatapathsthroughout,however,theexternalbuscanoperateinan8-bitnarrowmodesosingle8-bitwidememorycanbeinterfacedforlowercostsystems.TheinclusionofaPLLcircuitallowspowerconsumptionandperformancetobeadjustedtosuitoperationalrequirements.InadditiontotheI/Oportsavailableineachmodule,upto22I/OportsareavailablewithinterruptcapabilityallowingWake-UpfromSTOPorWAITmode.FeaturesNOTENotallfeatureslistedhereareavailableinallconfigurations.AdditionalinformationaboutDandBfamilyinter-operabilityisgivenin:EB386“HCS12D-FamilyCompatibilityConsiderations”andEB388“UsingtheHCS12D-FamilyasadevelopmentplatformfortheHCS12Bfamily”•16-bitCPU12—UpwardcompatiblewithM68HC11instructionset—Interruptstackingandprogrammer’smodelidenticaltoM68HC11—HCS12Instructionqueue—EnhancedindexedaddressingMultiplexedbus—Singlechiporexpanded—16address/16datawideor16address/8datanarrowmodes—Externaladdressspace1MByteforDataandProgramspace(112pinpackageonly)Wake-upinterruptinputsdependingonthepackageoption—8-bitportH—2-bitportJ1:0—2-bitportJ7:6sharedwithIIC,CAN4andCAN0module—8-bitportPsharedwithPWMorSPI1,2Memoryoptions—32K,64K,128K,256K,512KByteFlashEEPROM—1K,2K,4KByteEEPROM—2K,4K,8K,12K,14KByteRAMFreescaleSemiconductor,IFreescaleSemiconductor,Inc.ForMoreInformationOnThisProduct,Goto:Analog-to-DigitalConverters—Oneortwo8-channelmoduleswith10-bitresolutiondependingonthepackageoption—ExternalconversiontriggercapabilityUptofive1Mbitpersecond,CAN2.0A,Bsoftwarecompatiblemodules—Fivereceiveandthreetransmitbuffers—Flexibleidentifierfilterprogrammableas2x32bit,4x16bitor8x8bit—FourseparateinterruptchannelsforReceive,Transmit,ErrorandWake-up—Low-passfilterwake-upfunctioninSTOPmode—Loop-backforselftestoperationEnhancedCaptureTimer(ECT)—16-bitmaincounterwith7-bitprescaler—8programmableinputcaptureoroutputcomparechannels;4ofthe8inputcaptureswithbuffer—Inputcapturefiltersandbuffers,threesuccessivecapturesonfourchannels,ortwocapturesonfourchannelswithacapture/compareselectableontheremainingfour—Four8-bitortwo16-bitpulseaccumulators—16-bitmodulusdown-counterwith4-bitprescaler—Fouruser-selectabledelaycountersforsignalfiltering8PWMchannelswithprogrammableperiodanddutycycle(7channelson80PinPackages)—8-bit,8-channelor16-bit,4-channel—Separatecontrolforeachpulsewidthanddutycycle—Center-orleft-alignedoutputs—ProgrammableclockselectlogicwithawiderangeoffrequenciesSerialinterfaces—Twoasynchronousserialcommunicationsinterfaces(SCI)—Uptothreesynchronousserialperipheralinterfaces(SPI)—IICSAEJ1850CompatibleModule(BDLC)—10.4kbpsVariablePulseWidthformat—Bytelevelreceiveandtransmit—4xreceivemodesupportedSIM(SystemIntegrationModule)—CRG(windowedCOPwatchdog,realtimeinterrupt,clockmonitor,clockgenerationandreset)—MEBI(multiplexedexternalbusinterface)—INT(interruptcontrol)Clockgeneration—Phase-lockedloopclockfrequencymultiplier—Limphomemodeinabsenceofexternalclock—ClockMonitor—Lowpower0.5to16MHzcrystaloscillatorreferenceclockOperatingfrequencyforambienttemperaturesTA-40°C=TA=125°C—50MHzequivalentto25MHzBusSpeedforsinglechip40MHzequivalentto20MHzBusSpeedinexpandedbusmodes.Internal5Vto2.5VRegulator112-PinLQFPor80-PinQFPpackage—I/Olineswith5Vinputanddrivecapability—5VA/Dconverterinputsand5VI/O—2.5VlogicsupplyDevelopmentsupport—Single-wirebackgrounddebug™mode(BDM)—On-chiphardwarebreakpointsFreescaleSemiconductor,IFreescaleSemiconductor,Inc.ForMoreInformationOnThisProduct,Goto:Pinoutexplanations:—A/Disthenumberofmodules/totalnumberofA/Dchannels.—I/Oisthesumofportscapabletoactasdigitalinputoroutput.112PinPackages:PortA=8,B=8,E=6+2inputonly,H=8,J=4,K=7,M=8,P=8,S=8,T=8,PAD=16inputonly.22inputsprovideInterruptcapability(H=8,P=8,J=4,IRQ,XIRQ)80PinPackages:PortA=8,B=8,E=6+2inputonly,J=2,M=6,P=7,S=4,T=8,PAD=8inputonly.11inputsprovideInterruptcapability(P=7,J=2,IRQ,XIRQ)—CAN0pinsaresharedbetweenJ1850pins.—CAN0canbe