24位模数转换器ADS1210-11原理及应用

©1994-2010ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.(430074):224ADS1210/11,,:2A/DADS1210/111PGA-,,A/D(16bit,),A/D,,2A/D,ICAD,BB,TI2A/D,BBADS1210/11,A/D1ADS1210/11ADS1210/11Burr2Brown(BB)A/D,1ADS1210/112A/D,,2,,,,(,,,),+2.5V,313VADS1211,4ADS1210/11,1,2,4,8,16;TurboADS1210/11,TMR(TurboModeRate),;ADS1210/11,Hz16kHz;ADS1210/11,;ADS1210/11,,,ADS1210/11,,,,,,,,ADS1210/11,,,,,2ADS1210/11ADS1210/112A/D,,2A/D,2,,()2,,,(35199916262614462626145©1994-2010ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.),N,,,2A/D,A/D,3ADS1210ADS12102123456781112131415161718ADS1210APINANAGNDVBIASCSDSYNCXINXOUTININREFREFOUTMODEDRDYSDOUTSDIOSCLK910DGNDDDDV2DDAVAINP:AINN:AGND:VBIAS:CS:DSYNC:XIN:XOUT:1BYTE3BIASREFODFU/BBDMSBSDLDRDY0off1on0two0bip000defaultDGND:DVDD:,+5VSCLK:SDIO:/SDOUT:DRDY:MODE:/AVDD:,+5VREFOUT:+215VREFIN:4ADS1210/11ADS1210/11A/D,CPUMC(),MCALU,(INSR),(CMR),(OCR),(FCR),(DOR)INSR8,INSR,R/WMB1MB00A3A2A1A0R/W:/MB1MB0:A3A0:CMR32,ADS1210/11,1:BIAS:/REFO:/DF:U/B:(/)BD:MSB:SDL:DRDY:DRDYMD2MD0:G2G0:CH1CH0:SF2SF0:TMRdefault:(default)normal:gainl:channell:DR12DR0:23dbBYTE2MD2MD1MD0G2G1G0CH1CH0000normal000gain100channelldefaultBYTE1SF2SF1SF0DR12DR11DR10DR9DR8000TMR100000defaultBYTE0DR7DR6DR5DR4DR3DR2DR1DR000010111(23)defaultCMR:45:[phone]/222554419991©1994-2010ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.(a)4(66)(1)TMRGAIN16(2)DR12DR0(DecimationRate)23db,(fdata,:fdata=fXINTMR/(512DecimationRate)fdata,DecimationRate,DR12DR0:TMR=1,fXIN=10MHz,DR=0000000010111B(23),fdata=850HzOCRFCR,,DOR324,ADS1210/11,(Master)(Slave),,ADS1210/11,SCLK,,ADS1210/11XINMHz,DSP,;,SDIO,DSP,,,SCLKXIN,,SCLKXIN,3ADS1210/11,CS,SCLK,SDIOSDOUT,DRDYADS1210/11,,,,MC,SDIO,SDOUT,SCLK,SDIO,SDOUT,SCLK,CS,DRDY,ADS1210/11(),DRDY,:1)DRDYCMR,,2)DRDY,55199916257723062577231©1994-2010ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.:(1)I/O;(2)4I/O(1FCH1FFH);(3)8(,16);(4)874LS68874LS139;(5)74LS273FPGA(16);(6)74LS0074LS3274LS74FPGA(7)FPGAISA,ISAFP2GA(XCGCLK=PCCLK);(8)/ISA(PCCLK)412/5,,,1Xiilinx1TheProgrammableLogicDataBook,19962StephenTrimberger.FieldProgrammableGateArrays.IEEEDesign&TestofComputers,Sept.1992:3263JonathanRose.ArchitecureofField2ProgrammableGateAr2rays.ProceedingsoftheIEEE,Vol.81,No.7,July1993(:1998204230)(55),DOR1/fdata212(1/fXIN),,,DOR,ADS1210/11,,:TMR=1,fXin=10MHz,fdata=500Hz1215,,5ADS1210/118031ADS1210/11Slave80C31P110P1145ADS1210/11,+2.5V,XIN80C3174HC161ADS1210/11,SCLKXin41242BitANALOG2TO2DIGITALCONVERTER(BURR2BROWN)2,11:,1993(:1998205228)66:[phone]/222554419991