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AllegroSPBV16AdvanceAllegroSPBV16AdvanceAllegroSPBAllegroSPB16.216.2AdvanceAdvance¾ImportLogic¾BackAnnotate¾NetlistCompare¾AdvancedPlacement¾ConstraintManagement¾DifferentialPairImportLogic¾Other¾CadenceIImportLogicmportLogic––OtherOther•利用Other的方式轉出或者導入netlist的方式AllegroNetlist.netfileAllegroNetlistAllegroNetlist.netfileCadenceAllegroCadenceAllegroCadenceAllegroOrcadCaptureOrcadCaptureCISOrcadCaptureOrcadCaptureOrcadCaptureCISOrcadCaptureCISSchematicSchematicPCBlayoutPCBlayoutCreatenetlist(Otherallegro.dll)ImportLogic(Other)Device.txtfileDeviceDevice.txtfile+ExportLogic(Other)BackAnnotateCaptureBackAnnotation.swpfileCaptureCaptureBackAnnotationBackAnnotation.swpfile優點:在Capture中定義可以相對簡單缺點:導入netlist和回編線路圖對複雜,導入時需要Devicefile,回編時需要提供SwpfileIImportLogicmportLogic––OtherOther1.CreatenetlistfromCaptureToolsCreateToolsCreateNetlistNetlistOtherOther注意:在9.2版後,程式中已經沒有含allegro.dll必須在9.2之前的版本中allegro.dll複製到新的版本中放置的路徑home:\Cadence\SPB15.7\Capture\Netforms){PCBFootprint}!{PCBFootprint}Netlist格式:DeviceValuePartReferencenets利用Other的方式轉出或者導入netlist的方式AllegroNetlist格式:(其中[]的內容可以省略)[PCBFootprint]!Device![Value]![Tolerance];Reference2.ImportnetlisttoAllegro–OtherImportLogicOtherImportLogicOtherIImportLogicmportLogic––OtherOther•Syntaxcheckonly–只做語法check•Supersedealllogicaldata–取代現有的Logic•Appenddevicefilelog–將所有使用到的device加到netinlog•AllowetchremovalduringECO–當netlist有所變動時則會將相關的走線刪除•IgnoreFIXEDproperty–忽略Fixed設定•針對Cadence直接導入方式,簡稱新轉法CadenceAllegroCadenceAllegroCadenceAllegroOrcadCaptureOrcadCaptureCISOrcadCaptureOrcadCaptureOrcadCaptureCISOrcadCaptureCISSchematicSchematicPCBlayoutPCBlayoutCreatenetlist(CaptureAllegro)ImportLogic(CadenceCapture).brdBackAnnotate(Allegro)CreateupdateAllegroboardNetlistfiledirectoryPst*.datfilesNetlistNetlistfiledirectoryfiledirectoryPst*.datfilesIImportLogicmportLogic––CadenceCadence優點:Capture可以順利跟Allegro做雙向的溝通缺點:有條件規範Capture與Allegro的Lib直接開啟Allegro(參考ImportBoardFile將新資料寫入OutputBoardFile中)輸出netlist路徑IImportLogicmportLogic––CadenceCadence1.CreatenetlistfromCaptureToolsCreateToolsCreateNetlistNetlistAllegroAllegro•利用Allegro的方式轉出或者導入netlist的方式IImportLogicmportLogic––CadenceCadence2.ImportnetlisttoAllegro–AllegroImportLogicAllegroImportLogicAllegro•PropertyChanges•Ref-desChanges•PinanGateSwapsBackBackannotation(Cadenceannotation(Cadence))•PropertyChanges•Ref-desChanges•PinanGateSwapsBackBackannotation(Otherannotation(Other))DesignCompareDesignCompareTools\DesignCompare¾PlacementinAreas¾ALT_SYMBOL¾AssignRdfDes¾AutomaticSwappingofFunctionsandPinsAdvancedPlacement1.針對symbols2.針對board1.Shape–Polygon2.Class–BoardGeometrySubclass–Top_Room3.Edit–propertyRoom_Type當你轉netlist的方式是用CapturetoAllegro當你轉netlist的方式是用Other–Allegro.dllPlacementinAreasPlacementinAreas1.當你是用Netlist–Allegro轉Netlist2.當你是用Other–Allegro轉Netlist在在capturecapture中對中對partpart設定設定propertyproperty定義零件外型替換可在各零件的device檔中宣告可替換的零件外型語法為PACKAGEPROPALT_SYMBOLS'(Subclass:Symbol,...;Subclass:Symbol,...)'Subclass可為TOP或T指正面零件,BOTTOM或B指正面零件.若沒指定則視為正面.例如C0603可換成C0805或C1206(DEVICEFILE:C0603)PACKAGEC0603PACKAGEPROPALT_SYMBOLS'(C0805,C1206)'PINCOUNT2END在在DeviceFileDeviceFile中加入參數中加入參數ALT_SymbolALT_Symbol設定設定PlacePlace––ManuallyManually選擇滑鼠右鍵選擇滑鼠右鍵EditEdit––movemoveALT_SymbolALT_Symbol用法用法兩者的差別在於Place–有一個下拉式的選項讓你做選擇Move–漸進式的替換LogicLogic––AssignAssignRefDesRefDesAssignAssignRdfDesRdfDes先在Options中寫入要替換的RefDes在點選Board上遇替換的Symbol注意:替換的零件必須存在於Database中其腳Pin,電氣特性需要一致才可以互換¾Place–Swap–Pins¾Place–Swap–Functions¾Place–Swap–ComponentsSwappingofFunctionsandPinsSwappingofFunctionsandPins•當你是用Netlist–Allegro轉Netlist•當你是用Other–Allegro轉Netlist定義零件邏輯互換以DDR184為例宣告接點可互換為PINSWAP.宣告邏輯閘可互換則為各FUNCTIONGate(Devicefilefor7400)PACKAGEDIP14Packagename(PCBFootprint)CLASSICPlacementclassPINCOUNT14TotalnumberofpinsindevicePINORDER7400I0I1ODefinespinnamesforasectionPINUSE7400ININOUTSpecifiespinfunctions(relatestoPINORDER)PINSWAP7400I0I1SpecifiesswappablepinsFUNCTIONG17400123Definesasection(relatestoPINORDER)FUNCTIONG27400456DittoFUNCTIONG374009108DittoFUNCTIONG47400121311DittoPOWERVCC;14SpecifiespowerpinsGROUNDGND;7DittoENDSwappingPinsSwappingPinsPlace–Swap–Components‧需注意的事項‧Pin腳的數量‧電器的特性‧相同的包裝SwappingFunctionsSwappingFunctions定義零件邏輯互換以7400為例宣告接點可互換為PINSWAP.宣告邏輯閘可互換則為各FUNCTIONGate(Devicefilefor7400)PACKAGEDIP14Packagename(PCBFootprint)CLASSICPlacementclassPINCOUNT14TotalnumberofpinsindevicePINORDER7400I0I1ODefinespinnamesforasectionPINUSE7400ININOUTSpecifiespinfunctions(relatestoPINORDER)PINSWAP7400I0I1SpecifiesswappablepinsFUNCTIONG17400123Definesasection(relatestoPINORDER)FUNCTIONG27400456DittoFUNCTIONG374009108DittoFUNCTIONG47400121311DittoPOWERVCC;14SpecifiespowerpinsGROUNDGND;7DittoEND¾ConstraintManagement¾ConstraintManagementUI¾HierarchicalRuleManagementAHigh-SpeedDesignFlowAllegroDesignEntryTopologyEditorSchematicDatabaseBoardfileNetrevFront-to-backFlowPackagergenfeedExplorationDesignCaptureDesignRealizationAllegroPCBSIAllegroPCBEditorConstraintManagerTopologyEditorTopologyEditorBoardfileCMdatasigmodelsTopologyTemplatesElectricalCSetsSchematicViewConstraintViewSchematicDBConst
本文标题:allegro经典教程
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