DDS正弦波发生器源代码

包括：1.dds_vhdl.VHDL2.reg10b，reg32b.vhdl3.adder10b，adder32b.vhdl4.sin_rom.mif文件--%%%%%%%%%%%---dds_vhdl---%%%%%%%%顶层文件libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitydds_vhdlisPort(clk:instd_logic;fword:instd_logic_vector(7downto0);pword:instd_logic_vector(7downto0);fout:outstd_logic_vector(9downto0));end;architectureoneofdds_vhdliscomponentreg32bport(load:INstd_logic;din:INstd_logic_VECTOR(31downto0);dout:OUTstd_logic_VECTOR(31downto0));endcomponent;componentreg10bport(load:INstd_logic;din:INstd_logic_VECTOR(9downto0);dout:OUTstd_logic_VECTOR(9downto0));endcomponent;componentadder32bport(a:INstd_logic_VECTOR(31downto0);b:INstd_logic_VECTOR(31downto0);s:OUTstd_logic_VECTOR(31downto0));endcomponent;componentadder10bport(a:INstd_logic_VECTOR(9downto0);b:INstd_logic_VECTOR(9downto0);s:OUTstd_logic_VECTOR(9downto0));endcomponent;componentsin_romport(address:INstd_logic_VECTOR(9downto0);clock:INstd_logic;q:OUTstd_logic_VECTOR(9downto0));endcomponent;signalf32b,d32b,din32b:std_logic_vector(31downto0);signalp10b,lin10b,sin10b:std_logic_vector(9downto0);beginf32b(27downto20)=fword;f32b(31downto28)=0000;p10b(1downto0)=00;f32b(19downto0)=00000000000000000000;p10b(9downto2)=pword;u1:adder32bportmap(a=f32b,b=d32b,s=din32b);u2:reg32bportmap(dout=d32b,din=din32b,load=clk);u3:sin_romportmap(address=sin10b,q=fout,clock=clk);u4:adder10bportmap(a=p10b,b=d32b(31downto22),s=lin10b);u5:reg10bportmap(dout=sin10b,din=lin10b,load=clk);end;--%%%%%%%%%%%---sin_rom---%%%%%%%%LIBRARYieee;---sin_romUSEieee.std_logic_1164.all;LIBRARYaltera_mf;USEaltera_mf.all;ENTITYsin_romISPORT(address:INSTD_LOGIC_VECTOR(9DOWNTO0);clock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(9DOWNTO0));ENDsin_rom;ARCHITECTURESYNOFsin_romISSIGNALsub_wire0:STD_LOGIC_VECTOR(9DOWNTO0);COMPONENTaltsyncramGENERIC(address_aclr_a:STRING;init_file:STRING;intended_device_family:STRING;lpm_hint:STRING;lpm_type:STRING;numwords_a:NATURAL;operation_mode:STRING;outdata_aclr_a:STRING;outdata_reg_a:STRING;widthad_a:NATURAL;width_a:NATURAL;width_byteena_a:NATURAL);PORT(clock0:INSTD_LOGIC;address_a:INSTD_LOGIC_VECTOR(9DOWNTO0);q_a:OUTSTD_LOGIC_VECTOR(9DOWNTO0));ENDCOMPONENT;BEGINq=sub_wire0(9DOWNTO0);altsyncram_component:altsyncramGENERICMAP(address_aclr_a=NONE,init_file=sin_rom.mif,intended_device_family=Cyclone,lpm_hint=ENABLE_RUNTIME_MOD=NO,lpm_type=altsyncram,numwords_a=1024,operation_mode=ROM,outdata_aclr_a=NONE,outdata_reg_a=UNREGISTERED,widthad_a=10,width_a=10,width_byteena_a=1)PORTMAP(clock0=clock,address_a=address,q_a=sub_wire0);ENDSYN;--%%%%%%%%%%%---adder10b---%%%%%%%%libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityadder10bisPort(a,b:instd_logic_vector(9downto0);s:outstd_logic_vector(9downto0));endadder10b;architecturebehavofadder10bisbegins=a+b;endbehav;--%%%%%%%%%%%---adder32b---%%%%%%%%libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityadder32bisPort(a,b:instd_logic_vector(31downto0);s:outstd_logic_vector(31downto0));endadder32b;architecturebehavofadder32bisbegins=a+b;endbehav;--%%%%%%%%%%%---reg10b---%%%%%%%%libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityreg10bisPort(load:instd_logic;din:instd_logic_vector(9downto0);dout:outstd_logic_vector(9downto0));endreg10b;architecturebehavofreg10bisbeginprocess(load,din)beginif(load'eventandload='1')thendout=din;endif;endprocess;endbehav;--%%%%%%%%%%%---reg32b---%%%%%%%%libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityreg32bisPort(load:instd_logic;din:instd_logic_vector(31downto0);dout:outstd_logic_vector(31downto0));endreg32b;architecturebehavofreg32bisbeginprocess(load,din)beginif(load'eventandload='1')thendout=din;endif;endprocess;endbehav;--%%%%%%%%%%%---sin_rom.mif---%%%%%%%%WIDTH=10;DEPTH=1024;ADDRESS_RADIX=DEC;DATA_RADIX=DEC;CONTENTBEGIN0:512;1:515;2:518;3:521;4:524;5:527;6:530;7:533;8:537;9:540;10:543;11:546;12:549;13:552;14:555;15:559;16:562;17:565;18:568;19:571;20:574;21:577;22:580;23:583;24:587;25:590;26:593;27:596;28:599;29:602;30:605;31:608;32:611;33:614;34:617;35:621;36:624;37:627;38:630;39:633;40:636;41:639;42:642;43:645;44:648;45:651;46:654;47:657;48:660;49:663;50:666;51:669;52:672;53:675;54:678;55:681;56:684;57:687;58:690;59:693;60:696;61:699;62:701;63:704;64:707;65:710;66:713;67:716;68:719;69:722;70:725;71:727;72:730;73:733;74:736;75:739;76:741;77:744;78:747;79:750;80:753;81:755;82:758;83:761;84:764;85:766;86:769;87:772;88:774;89:777;90:780;91:782;92:785;93:788;94:790;95:793;96:796;97:798;98:801;99:803;100:806;101:809;102:811;103:814;104:816;105:819;106:821;107:824;108:826;109:829;110:831;111:834;112:836;113:838;114:841;115:843;116:846;117:848;118:850;119:853;120:855;121:857;122:860;123:862;124:864;125:866;126:869;127:871;128:873;129:875;130:878;131:880;132:882;133:884;134:886;135:888;136:890;137:893;138:895;139