FPGA综合设计实例

第十章综合设计实例1键盘扫描与显示•矩阵式键盘:行,列矩阵是键盘以行列形式排列，键盘上每个按键其实是一个开关电路，当某键被按下时，该按键对应的位置就呈现逻辑0状态.行扫描方式:逐行送0电平,读取列的状态,以判断按下的键号.列扫描方式:逐列送0电平,读取行的状态,以判断按下的键号.以行扫描为例:1给行依次送0111,1011,1101,1110信号;2读取列电平状态,数码管显示•libraryieee;•useieee.std_logic_1164.all;•useieee.std_logic_unsigned.all;•entitykey_scanis•port(column:instd_logic_vector(3downto0);--列状态•scan_cnt:instd_logic_vector(3downto0);---扫描字•row:outstd_logic_vector(3downto0);---行状态•key_pressed:outstd_logic);-----按键有效与否,后续判断为零则为有键按下•end;•architecturertlofkey_scanis•begin•row=1110whenscan_cnt(3downto2)=00else•1101whenscan_cnt(3downto2)=01else•1011whenscan_cnt(3downto2)=10else•0111;•key_pressed=column(0)whenscan_cnt(1downto0)=00else•column(1)whenscan_cnt(1downto0)=01else•column(2)whenscan_cnt(1downto0)=“10else•column(3);•endrtl;按键扫描控制程序按键处理控制模块•libraryieee;•useieee.std_logic_1164.all;•useieee.std_logic_unsigned.all;•useieee.std_logic_arith.all;•entityscan_countis•port(clk:instd_logic;--clock•scan_clk:instd_logic;--1khzclk•key_pressed:instd_logic;--检测按键有效与否,停止计数.•scan_cnt:outstd_logic_vector(3downto0));--计数•end;•architecturebehavofscan_countis•signalqscan:std_logic_vector(3downto0);•begin•scan_1:process(clk,scan_clk,key_pressed)•begin•if(clk'eventandclk='1')then•if(scan_clk='1'andkey_pressed='1')then•qscan=qscan+1;endif;endif;•endprocess;•scan_cnt=qscan;end;按键消抖控制模块•libraryieee;•useieee.std_logic_1164.all;•useieee.std_logic_unsigned.all;•useieee.std_logic_arith.all;•entitydebounceis•port(key_pressed:instd_logic;•clk:instd_logic;--同步时钟•scan_clk:instd_logic;--1khzclock•key_valid:outstd_logic);•end;•architecturebehavofdebounceis•begin••debounce:process(clk,scan_clk,key_pressed)•variabledbnq:std_logic_vector(5downto0);•begin•if(key_pressed='1')then•dbnq:=111111;--unkey_pressed,countresetat63•elsif(clk'eventandclk='1')then•ifscan_clk='1'then•ifdbnq/=1then•dbnq:=dbnq-1;--key_pressednotenoughlongtime•endif;endif;endif;•ifdbnq=2then•key_valid='1';--key_validafterkey_pressed1/63ksecond•else•key_valid='0';•endif;•endprocess;•end;键盘译码及按键存储模块•libraryieee;•useieee.std_logic_1164.all;•useieee.std_logic_unsigned.all;•useieee.std_logic_arith.all;•entitycode_tranis•port(clk:instd_logic;--clockforsynchrony•scan_cnt:instd_logic_vector(3downto0);--1khzclock•key_valid:instd_logic;•butt_code:outstd_logic_vector(3downto0));•end;•architecturebbofcode_tranis•begin•process(clk)•begin•if(clk'eventandclk='1')then•ifkey_valid='1'then•casescan_cntis•when0000=butt_code=0001;--1•when0001=butt_code=0010;--2•when0010=butt_code=0011;--3•when0011=butt_code=1100;--c•when0100=butt_code=0100;--4•when0101=butt_code=0101;--5•when0110=butt_code=0110;--6•when0111=butt_code=1101;--d•when1000=butt_code=0111;--7•when1001=butt_code=1000;--8•when1010=butt_code=1001;--9•when1011=butt_code=1110;--e•when1100=butt_code=1010;--a•when1101=butt_code=0000;--0•when1110=butt_code=1011;--b•whenothers=butt_code=1111;--f•endcase;•endif;endif;•endprocess;end;电锁控制模块libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityctrlisport(data_n:instd_logic_vector(3downto0);key_valid,clk:instd_logic;enlock:outstd_logic;d,c,b,a:outstd_logic_vector(3downto0));end;architectureaaaofctrlissignalacc,reg:std_logic_vector(15downto0);signalnc:std_logic_vector(2downto0);signalqa,qb:std_logic;beginkeyin:blockisbeginprocess(data_n,key_valid)beginifdata_n=1101thenacc=0000000000000000;nc=000;elsifkey_valid'eventandkey_valid='1'thenifdata_n1101thenifnc=4thenacc=acc(11downto0)&data_n;nc=nc+1;endif;endif;endif;endprocess;endblock;lock:blockisbeginprocess(clk,data_n)beginif(clk'eventandclk='1')thenifnc=4thenifdata_n=1110thenreg=acc;qa='1';qb='0';elsifdata_n=1111thenifreg=accthenqa='0';qb='1';endif;endif;endif;endif;endprocess;endblock;•enlock=qaandnotqb;•d=acc(15downto12);•c=acc(11downto8);•b=acc(7downto4);•a=acc(3downto0);•endaaa;动态扫描显示控制模块libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitysel_displayisport(clk:instd_logic;d,c,b,a:instd_logic_vector(3downto0);db_out:outstd_logic_vector(3downto0);dis_out:outstd_logic_vector(3downto0));endentity;architecturertlofsel_displayissignalsel:std_logic_vector(1downto0);signaldis:std_logic_vector(3downto0);signaldb:std_logic_vector(3downto0);begincounter:blockissignalq:std_logic_vector(6downto0);beginprocess(clk)beginifclk'eventandclk='1'thenq=q+1;endif;endprocess;sel=q(1downto0);endblockcounter;multiplexer:blockisbeginprocess(sel)beginifsel=0thendb=d;dis=0111;elsifsel=1thendb=c;dis=1011;elsifsel=2thendb=b;dis=1101;elsifsel=3thendb=a;dis=1110;endif;endprocess;endblockmultiplexer;db_out=db;dis_out=dis;endrtl;实例1数字钟设计实时显示时、分、秒分析：1、最小计时单位：秒。因此，首先要由时钟产生1HZ的信号；2、对秒进行0-59的计数，并且有进位功能，且显示；3、对分进行0-59的计数，并且有进位功能，且显示；4、对时进行0-59的计数，且显示；libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.allentitysecondisport(clk,clr:instd_logic;--clk=1Hzsec1,sec0:outstd_logic_vector(3downto0);co:outstd_logic);endsecond;architecturearchofsecondisbeginprocess(clk,clr)variablecnt1,cnt0:std_logic_vector(3downto0)