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FreescaleSemiconductorApplicationNote©FreescaleSemiconductor,Inc.,2008.Allrightsreserved.Thisapplicationnoteisadesignguidetoassistthecustomerincreatingalow-layer,low-cost,PCBdesignwhenusingtheMPC8544Edevice.KeyitemsofdiscussionincludeassumedPCBstackup,powerdelivery,andpropersignalreferencing.Additionally,layoutplotsforthedevicefan-outarealsoincluded.NOTETheschematicandGerberdatashownwithinthisapplicationnoteareintendedmerelytodemonstratethefan-outandpowerdeliverystrategynecessarytoachieveasix-layerPCB.TheschematicandGerberdatadoesnotincludeallthedecoupling,nordotheyshowallthenecessarypull-upsandACcapsrequiredoutsidetheBGAfan-outarea.ThislevelofdetailiscapturedaspartoftheMPC8544Edevelopmentsystem.DocumentNumber:AN3535Rev.0,2/2008Contents1.References..................................22.BallmapOrganization.........................23.InterfaceSupportinSixLayers.................34.BoardStackupConsiderations..................45.SignalBreakout..............................66.ViaUsage..................................97.PowerandGroundStrategy...................108.SignalLayerGerberPlot.....................209.Fan-OutSchematics.........................2410.CurrentDeliveryintheBGAField..............3911.RevisionHistory............................43AStrategyforRoutingtheMPC8544EinaSix-LayerPCBbyMichaelGeorgeNMGApplicationsFreescaleSemiconductor,Inc.Austin,TexasAStrategyforRoutingtheMPC8544EinaSix-LayerPCB,Rev.02FreescaleSemiconductorReferences1ReferencesTable1listsreferencesmentionedinthisapplicationnote,aswellasusefulresourcesforfurtherreading.2BallmapOrganizationTheMPC8544Eisa783-pin,28×28BGAarray.ThebusorganizationofthedeviceisshowninFigure1.Figure1.MPC8544EBusGroupings(viewedfromthetopofthedevice)Table1.ReferencesDocumentSourceIPCStandards:IPC-D-275IPC-2221AIPC-2152www.ipc.orgNewCorrelationsBetweenElectricalCurrentandTemperatureRiseinPCBTracesJohannesAdam,FlomericsLtd.20thIEEESEMI-THERMSymposium0-7803-8363-X/04/$20.00©2004IEEEwww.flomerics.com/flotherm/technical_papers/t341.pdfCurrent-CarryingCapacity,MartinTarr,UniversityofBoltonwww.ami.ac.uk/courses/ami4817_dti/u02/pdf/meah0221.pdfInteractivetrace-widthcalculator,Rev.0FreescaleSemiconductor3InterfaceSupportinSixLayers3InterfaceSupportinSixLayersThoughtheMPC8544Edevicecanbefullybrokenoutinsixlayers,thereareahandfulofsignalsthatarenotnecessarilyoptimalfromasignalintegrityperspective,mainlyduetosplitsinthereferenceplane.Suchcasesareverylimitedandare,therefore,manageable.Table2enumeratestheMPC8544Einterfacesandindicateswhetherthereispropersignalreferencinginthesix-layerPCBfan-outexample.Table2.InterfaceSupportinSixLayersInterfaceConfigurationReferencePlaneCommentDDR2Full64-bit+ECCDDRData—GNDDDRADDR—1.8VDDRCLKs—1.8VFullysupported.ETSECRGMIIRGMIII/O—2.5VGTX_CLK125—GNDBothEthernetportscanbefullybrokenoutinRGMIImode.Somesignalscrosssplitboundaries;therefore,stitchingcapswouldlikelybebeneficial.PORConfigAlluserdefinedPORpinsareaccessible.GNDandPWRFullysupported.SomePORpinscrosssplitboundaries,butbecausetheyarestatic,thereisnoconcern.PCIFull32-bitPCIGNDandPWRLBAllsignalsareaccessibleGNDandPWRLB_LAD[23:31]crosssplitboundaries.Thesesignalsarenotedgesensitive,thereforeimperfectionsintheirtransitionscanbemanaged.Useofstitchingcapscouldbeused.SERDES1AlleightlanesaccessibleGNDFullysupportedSERDES2BothlanesaccessibleGNDFullysupportedIRQAllIRQs(0–11)andIRQ_OUTusableGNDandPWRFullysupportedJTAG/COPAllsignalsareaccessibleGNDandPWRFullysupportedDUARTSBothUARTportsarefullyaccessibleGNDandPWRFullysupportedPowerpinsandAVDDfiltersAlluniquepowersaccessibleN/AFullysupportedI2CBothI2CportaccessibleGNDandPWRFullysupportedClockingSYSCLKandRTCaccessibleGNDandPWRFullysupportedAStrategyforRoutingtheMPC8544EinaSix-LayerPCB,Rev.04FreescaleSemiconductorBoardStackupConsiderations4BoardStackupConsiderationsThissectionpresentstheconsiderationsassociatedwiththePCBanditsstackup.Table3liststhetargetimpedancesneededinasix-layerdesign.Additionalconsiderationsforthestackupinclude•Mustutilizehigh-volume,low-cost,PCBtechnology�Routingdensity�Aspectratiolessthan10:1�Drillsizesetat10mil�Commoncoreconstruction�Propersignalreferencingforallcriticalsignals4.1StackupProposalFigure2showsaviablestackupforachievingthetargetimpedancesnotedinTable3.Thetargetcardthicknessusedis62mils(±7mils).Allsignalroutingisdoneontheinnertwosignallayers,oronthetopandbottomsignallayers.Nosignalroutingisperformedonthepowerandgroundlayers.Table3.TargetImpedanceforaTypicalMPC8544EDesignInterfaceConnectionTargetImpedanceDDR2MPC8544E-to-DDR2memorySingle-endedimpedance=55–60ΩDifferentialimpedance=100Ω±10%SERDES1(PCIe)MPC8544E-to-PCIeconnectorordeviceMicrostripSingle-endedimpedance=60±15%Differentialimpedance=100Ω±20%StriplineSingle-endedimpedance=60±15%Differentialimpedance=100Ω±15%SERDES2(SGMII/PCIe)MPC8544E-to-connectorordeviceMicrostripSingle-endedimpedance=60±15%Differ