数字跑表VerilogHDL程序

数字跑表VerilogHDL程序顶层模块modulepaobiao(CLK,CLR,PAUSE,CLK,CLK1);inputCLK,CLK1;//100Hz基准时钟，1kHz数码管扫描时钟inputCLR,PAUSE;output[3:0]MSH,MSL,SH,SL,MH,ML;reg[3:0]MSH,MSL,SH,SL,MH,ML;wire[3:0]dec_in;jishijishi(CLK,CLR,PAUSE,MSH,MSL,SH,SL,MH,ML);count10count10(CLK,CLK1);decode4_7decode4_7(decodeout,dec_in);segscansegscan(dec_in,MSL,MSH,SL,SL,ML,MH);endmodule时基分频器模块modulecount10(CLK,CLK1);inputCLK1;outputCLK;reg[4:0]qout;always@(posedgeCLK1)beginif(qout9)qout=qout+1;elseqout=0;endassignCLK=(qout==9)?1:0;endmoduleregCLK1;reg[4:0]qunt;always@(posedgeCLKornegedgeRST)//异步清零beginif(~rst)beginqunt=5'd0;endelseif(qunt==5'd9)beginqunt=5'd0;endelsebeginqunt=qunt+1'b1;endendwireCLK1;assignCLK1=qunt[4];计时器模块/*信号定义CLK：时钟信号；CLR：异步复位信号；PAUSE：暂停/启动信号；MSH，MSL：百分秒的高位和低位；SH，SL：秒信号的高位和低位；MH，ML：分钟信号的高位和低位。*/modulejishi(CLK,CLR,PAUSE,MSH,MSL,SH,SL,MH,ML);inputCLR,CLK,PAUSE;output[3:0]MSH,MSL,SH,SL,MH,ML;reg[3:0]MSH,MSL,SH,SL,MH,ML;regcn1,cn2;//cn1为百分秒向秒的进位，cn2为秒向分的进位//**********百分秒计数进程，每计满100，cn1产生一个进位1**********always@(posedgeCLKorposedgeCLR)beginif(CLR)begin//异步复位{MSH,MSL}=8'h00;cn1=0;endelseif(!PAUSE)//PAUSE为0时正常计数，为1时暂时计数beginif(MSL==9)//百分秒低位是否为9beginMSL=0;if(MSH==9)beginMSH=0;cn1=1;endelseMSH=MSH+1;cn1=0;endelsebeginMSL=MSL+1;cn1=0;endendend//**********秒计数进程，每计满60，cn2产生一个进位**********always@(posedgecn1orposedgeCLR)beginif(CLR)//异步复位begin{SH,SL}=8'h00;cn2=0;endelseif(SL==9)//低位是否为9beginSL=0;if(SH==5)beginSH=0;cn2=1;endelseSH=SH+1;cn2=0;endelsebeginSL=SL+1;cn2=0;endend//**********分钟计数进程，每计满60，系统自动清零**********always@(posedgecn2orposedgeCLR)beginif(CLR)//异步复位begin{MH,ML}=8'h00;endelseif(ML==9)beginML=0;if(MH==5)beginMH=0;endelseMH=MH+1;endelseML=ML+1;endendmodule数据选择模块modulesegscan(dec_in,MSL,MSH,SL,SL,ML,MH)output[3:0]dec_in;input[2:0]MSL,MSH,SL,SL,ML,MH;reg[3:0]MSL,MSH,SL,SL,ML,MH;always@(posedgeCLK1)beginif(ss3'd7)ss=0;elsess=ss+1;endalways@(posedgeCLK1)begincase(ss)3'd5:dec_in=MSL;3'd4:dec_in=MSH;3'd3:dec_in=SL;3'd2:dec_in=SH;3'd1:dec_in=ML;3'd0:dec_in=MH;3'd6:dec_in=3'd0;3'd7:dec_in=3'd0;endcaseendendmoduleBCD/七段译码模块moudledecode4_7(decodeout,dec_in)input[3:0]dec_in;output[6:0]decodeout;reg[6:0]decodeout;always@(dec_in)//用case语句进行译码begincase(dec_in)//decodeout[6]~[10]分别对应数码管的a~g4'd0:decodeout=7'b00111111;//显示04'd1:decodeout=7'b00000110;//显示14'd2:decodeout=7'b01011011;4'd3:decodeout=7'b01001111;4'd4:decodeout=7'b01100110;4'd5:decodeout=7'b01101101;4'd6:decodeout=7'b01111101;4'd7:decodeout=7'b00000111;4'd8:decodeout=7'b01111111;4'd9:decodeout=7'b01101111;default:decodeout=7'bx;endcaseendendmodule