MIPI Specification for RFFE

MIPIAllianceSpecificationforRFFEOutlineOverviewDefinitionsRFFEinterfaceandBusStructureOperatingStatesPhysicalLayerI/OStructuresI/OVoltageProtocolLayerCommandSequencesErrorDetectionandHandlingSlaveDeviceAddressMappingDeviceEnumerationDefinitionsMIPI:MobileIndustryProcessorInterfaceRFFE:RFFront-EndControlInterfaceRFFEisatwo-wires,serialinterfaceintendedtobeusedtoconnectRadioFrequencyICsofamobileterminaltotheirrelatedFront-EndModules.Two-wires:SCLK,RFFEclocksignal,drivenbytheMaster.SDATA,RFFEdatasignal,bidirectional,drivenbytheMasteroraSlave.RFFEInterfaceandBusStructureNMaxis15Figure1RFFEInterfaceandBusStructureRFFEClock(SCLK)TheMasterdrivetheSCLK,allclockwaveformsshallstartandendwiththeSCLKsignalatlogiclevelzero.SCLKshallnottoggleduringidleandinactivetimeperiod.SCLKshallonlyrunwhiledataisbeingtransferredonthebus,otherwiseSCLKisatlogiclevelzero.ThemaximumoperationfrequencyofSCLKis26MHz.FullSpeed:SCLKfrequencybetween13MHzand26MHz.HalfSpeed:SCLKfrequencybetween32kHzand13MHz.SpecificationsforSCLKInputFigure2ReceivedClockSignalConstraintsTable2ClockInputTimingRequirementsRFFEData(SDATA)TheRFFESDATAsignalisbidirectional,drivenbytheMasteroraSlave.WritethedataontherisingedgeofSCLKsignal.ReadthedataonthefallingedgeoftheSCLKsignal.FortheSlave,theread-backfunctionisoptional.SDATADriverTable3SDATAOutputTimingCharacteristicsTDTDTSDATAOTRVTPmaxSCLKVTNminVOHminVOLmaxSDATATSDATAOTRFigure3BusActiveDataTransmissionTimingSpecificationSDATAReceiverTable4DataSetupandHoldTimingFigure4BusActiveDataReceiverTimingRequirementsOperatingStateSlavesshallhaveaminimumofthreeoperatingstates,ACTIVE,SHUTDOWNandSTARTUP.AnoptionalfourthLOWPOWERstateisshowninFigure5.Figure5SlaveStateDiagramOutlineOverviewDefinitionsRFFEinterfaceandBusStructureOperatingStatesPhysicalLayerI/OStructuresI/OVoltageProtocolLayerCommandSequencesErrorDetectionandHandlingSlaveDeviceAddressMappingDeviceEnumerationSDATAI/OStructuresFigure6SDATAMasterandSlaveI/OCellsFigure7SDATAMasterandSlaveI/OCellsforanNon-readbackCapableSlaveSCLKI/OStructuresFigure8SCLKMasterandSlaveI/OCellsNote:SDATAandSCLKpull-downsmaybeimplementedasinternalorexternalcomponentsorcurrentsources.Internalpull-downsshallbeimplementedonlyonaMaster.TheI/Ocellshallbeimplementedwithhighimpedanceinputstructuresandoutputdriversthatarehighimpedancewhennotactive.I/OVoltageAllcomponentsonasingleRFFEbusinstanceshallsharethesameI/Ovoltagelevelfromacommonsource.TheVIOsignalisprovidedbytheMaster.TheVIOsignalisprovidedbyanexternalreferencevoltagesource.Figure9VIOBusSupplyFigure10VIOExternalBusSupplySlaveVIODigitalTheSlavedigitallogicoperatesatVIO.TheregisterresetsignalisgeneratedbytheVIOinputsignal.Voltageleveltranslationmaybedoneataninternalblockinterfacelevel.IsolationbetweenVIOandVregpowerisnecessary.Figure11SlaveVIODigitalSlaveVregDigitalTheSlavedigitallogicoperatesatVreg.Voltageleveltranslationisdoneatthepadinterfacelevel.IftheVregisalwaysonbeforetheVIO,theregisterresetisgeneratedwithinthedigitalblock(ResetD).IftheVregisnotalwaysonbeforetheVIOispoweredaregisterresetmayneedtobeprovidedfromtheVregfunctionalblock(ResetA).Figure12SlaveVregDigitalI/OVoltageSupplyPinRequirementsTable5VIOSupplyPinRequirementsOutlineOverviewDefinitionsRFFEinterfaceandBusStructureOperatingStatesPhysicalLayerI/OStructuresI/OVoltageProtocolLayerCommandSequencesErrorDetectionandHandlingSlaveDeviceAddressMappingDeviceEnumerationCommandSequencesBitOrdering:MSBfirstFormofCommandSequence:SSC,FramesandBusParkCycleSSC:SequenceStartCondition.TherearethreebasictypesofFrames:CommandFrame,thirteenbits.DataorAddressFrames,ninebits.NoResponseFrame,ninebits.ParityBitAFrameshallendwithasingleparitybit.TheparitybitshallbedrivensuchthatthetotalnumberofbitsintheFrametherearedriventologiclevelone,includingtheparitybit,isodd.BusParkCycleAdevicewithownershipofSDATAshallinitiateaBusParkCycleonSDATAattheendofaCommandSequenceorwhenthedevicetransferscontrolofSDATAtoanotherdevice.DuringtheBusParkCycle,thedevicereleasingSDATAshalldrivetheSDATAsignaltologiczeroduringthefirsthalfoftheSCLKclockcycle,thereafter,putitsdriverintohighimpedancestate.SSCSSC:SequenceStartCondition.TheMastershallgeneratetheSSCbyarisingedgefollowedbyafallingedgeonSDATAwhileSCLKremainatalogiclowlevelasshowninFigure13.Figure13SequenceStartConditionCommandFrameACommandFrameshallconsistofa4-bitSlaveaddressfield,an8-bitcommandpayloadfieldandasingleparitybitasshowninFigure14.Figure14CommandFrameDataorAddressFrameADataorAddressFrameshallconsistofeightdatabitsoreightaddressbits,respectively,andasingleparitybit.TheFrameiscalledanAddressFramewhenthepayloadbitscarriedaddressinformation.TheFrameiscalledaDataFramewhenthepayloadbitscarrieddatainformation.Figure15DataorAddressFrameNoResponseFrameAllbits,includingtheparitybit,ofaNoResponseFrameshallbezero.ItmaybegeneratedbydrivingSDATAtologiclevelzeroorpassivelyallowingtheMastertopullSDATAlowforthedurationoftheFrame.ItisusedastheresponseofawriteonlySlaveduringaReadCommandSequence,orbyaSlavedur