电荷泵PLL中PFD的设计

30220074ChineseJournalOfElectronDevicesVol.30No.2Apr.2007DeignofPFDinCP2PLLCircuitsWANGXiao2wei1,WUJin1,LUShen2li1,HUANGJin2sheng1(ICInstituteofSoutheastUniversity,Nanjing210096,China)Abstract:Basedontheanalysisofprincipleofcharge2pumpPhaselockedLoop,thePFD,whichisoneofthecriticalbuildingblocksinCP2PLL,iscomprehensivelyanalyzedintheoryanddesigned.ThecircuitcanquicklytrackfrequencyunderanyfrequencyerrorsinthedynamicrangeofVCO,andfinally,achievephaselocked.ComparedtogeneralPD,ithasamuchlargerphaserange(-2+2)ofoperationandzerooff2setofphase.ThesimulationresultswhichbasedontheCSMC0.5mmixedsignalCMOStechnologybyHSPICEcandeliverupto5/4V/radgainat27MHz/sreferencefrequencyand5Vpower.Keywords:phase2lockedloop;phasefrequencydetector;frequency/phaselocking;chargepump;EEACC:2570PLLPFD1,1,1,1(IC,210096):2006206201:(19822),,,PLL,[e-mail];(19652),,,,[e-mail];(19652),,,,[e-mail]:CP2PLL,(PFD).VCO,,.,PFD(-2+2),.0.5mCMOSHSPICE,5V27MHz/s,PFDKpd5/4V/rad.:;;/;:TN402:A:100529490(2007)0220503204PLL,.CP2PLL(PFD)(CP)(LPF)(VCO)[1].,,VCO.PLL,1[2],(PFD),,[3].PFDPLL,PFD,,0.5mCMOS,27Mhz/s1,.1PFD1.1PFDPLL,1:,,.PFDVref,Vosc,,PFD,,LPF,VCOVoscVCO,PFD,,,,.1.2PFD2,Vref,VoscVCO,up,down.,2.VrefVosc,Vref2PFD,up,Vosc,down,,D,updown.Vosc,Vref.,001001,updown11,00.VCOVrefVosc,up,VrefVosc,down,VrefVosc,,.,up,0.5,down,VrefVosc,,[4].PFDPD.,PFDPD,PFD-2+2,PD;,PFDVCO,PuPd,,.,|2|,.,.,PFD,,VCO,.PFD2,RSLatch,RSLatch.VrefPuVoscPdRSLatch.PFD,PuPd.,PuVref,PuPMOS,Vosc;PdVosc,PdNMOS,,Vosc.PFD,VdVCO,,VCO.,,,VdVCO.PFD1.1PFDPu/PubPdPUPD11/0000+120/1010030/1111-141/0101-0Pu=Pd=1,(3).PMOS,Pu,Pd,.Pu=1Pub40530=0,Pd,[PD]=0,[PU]=0(Pu=1)[PD]=1,,[PU]=1[PD]=0.3PFDPFD,Reset1Reset2,Reset1Reset2,Q1b=Pu=0,Q2b=Pd=0,PU=1PD=00,2.,,Pub=1Pdb=1.,VR=0,Q1=Q2=1;,Pub=Pdb=0,4,VR=1,Q1=Q2=0.,,PUPD,Q1Q2PubPdb.[Reset]=0,PFDVref,Vd,-1v0v+1,+1,Vref,+1,Vosc.Vosc,Vd,+1v0v-1,-1Vosc,-1,Vosc.,VrefVd,,Vosc,.,,Vd(0).,2,0.,.,VrefVosc,0,.4,Pu=Pd=1.Pu=1,Pub=Q1b=[Reset]=0,Pd=1,Pdb=Q2b=[Reset]=0,Pu=Pd=1Q1b=Q2b=Pub=Pdb=0,,1,[Reset]=1PFD0,0,[Reset]=1,[Reset]=00.,,0.,PFD4[5].4PFDPFD..0,a(b=0),+1,,b=1b,-1,,.,ab,0.,.ab,.,ab,Reset,0.,PFDVCO,,[6].227MHz/s,Reset,Verf,Vsoc,PUPD.PFD5.56:VrefVosc,PLL;f0VCOfosc,VrefVosc,PD,PU;f0fosc,VrefVosc,PU,PD;f05052,:PLLPFDfosc,PU,PD.PU,VCO,VCO;f0fosc,PD,PU.PD.56PFD,-7,PFDKpd=(Voh2Vol)/4=5/4,4,EXOR,JK2.0[7](DeadZone).8,,,.PFD,PFD.PFD-..7PFD283,:,[8],CPPLL,,,PLL,,PD.:[1]StephenWilliams,HughThompson,MichaelHufford,EricNa2viasky.AnImprovedCMOSRingOscillatorPLLwithLessthan4psRMSAccumulatedJitter[C]//IEEECICC2004,1512154.[2]BehzadRazavi.DesignofAnalogCMOSIntegratedCircuits[M].XianJiaotongUniversityPress,2003,4332470.[3]LeeJon2Ho,HanSeon2Ho,YooHoi2Jun.A330MHzLow2JitterandFast2LockingDirectSkewCompensationDLL[C]//ISSCC,Feb.2000,21(3):3512353.[4]RolandE.Best,Phase2LockedLoopsDesign,Simulation,andApplications[M].,2003,19224,77279.[5]MasoudKarimi2Ghartemani,HoushangKarimi,andM.RezaIravaniAMagnitude/Phase2LockedLoopSystemBasedonEs2timationofFrequencyandIn2Phase/Quadrature2PhaseAmpli2tudes[J].IEEEAPRIL,2004.51(2):5112517.[6]RobertoNonis,NicolaDaDalt,PierpaoloPalestri.Modeling,DesignandCharacterizationofaNewLow2JitterAnalogDualTuningLC2VCOPLLArchitecture[J].IEEEJ,SSC,June.2005,40(6):130321309.[7]johnsDavidA,KenMartin.AnalogIntegratedCircuitDesign[M].,2005,4652480.[8],,.CMOSPLL[J].,2000,25(3):30237.60530