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moduleDig_clk(inputCLK_50M,inputCLK_1HZ,inputCLK_1K,inputRSTN,inputselec,inputSET_add,//inputSET_sub,output[23:0]time_value,output[3:0]LED);wireCLK_1S;wire[7:0]hour,min,sec;assignLED=~mode;wire[3:0]mode;set_timeD1(.RSTN(RSTN),.TURN(selec),.flag(mode));wirevalue0,value1,value2;mode_selD2(.set_add(SET_add),.CLK(CLK_1HZ),.mode(mode[2]),.value(value2));wireCLK_min,CLK_h;sec_bitD3(.CLK_1S(value2),.RSTN(RSTN),.sec(sec),.CLK_min(CLK_min));mode_selD4(.set_add(SET_add),.CLK(CLK_min),.mode(mode[1]),.value(value1));min_bitD5(.CLK_min(value1),.RSTN(RSTN),.min(min),.CLK_h(CLK_h));mode_selD6(.set_add(SET_add),.CLK(CLK_h),.mode(mode[0]),.value(value0));hour_bitD7(.CLK_h(value0),.RSTN(RSTN),.hour(hour),);assigntime_value=hour*10000+min*100+sec;endmodulemoduleset_time(inputRSTN,inputTURN,outputreg[3:0]flag);always@(posedgeTURNornegedgeRSTN)beginif(~RSTN)flag=4'b1000;elseflag={flag[2:0],flag[3]};endendmodulemodulemode_sel(inputCLK,inputset_add,inputmode,outputvalue);assignvalue=(mode)?set_add:CLK;endmodulemodulesec_bit(inputCLK_1S,inputRSTN,outputreg[7:0]sec,outputregCLK_min);always@(posedgeCLK_1SornegedgeRSTN)beginif(!RSTN)sec=0;elseif(sec==8'd59)beginsec=0;CLK_min=1;endelsebeginsec=sec+1;CLK_min=0;endendendmodulemodulemin_bit(inputCLK_min,inputRSTN,outputreg[7:0]min,outputregCLK_h);always@(posedgeCLK_minornegedgeRSTN)beginif(!RSTN)min=0;elseif(min==8'd59)beginmin=0;CLK_h=1;endelsebeginmin=min+1;CLK_h=0;endendendmodulemodulehour_bit(inputCLK_h,inputRSTN,outputreg[7:0]hour);always@(posedgeCLK_hornegedgeRSTN)beginif(!RSTN)hour=0;elseif(hour==8'd23)hour=0;elsehour=hour+1;endendmodulemodulelab4_top(inputCLK_50M,inputRSTN,//inputmode,//input[23:0]num_out,outputwire[2:0]sel_out,outputwire[7:0]seg,output[3:0]LED,inputTURN,inputSET_add//inputSET_sub);wireCLK_1HZ;wireCLK_1KHZ;wire[23:0]num_out;//wire[3:0]data_num;wire[23:0]time_value;wire[23:0]num_value;sys_clkU1(.CLK(CLK_50M),.RSTN(RSTN),.CLK_1K(CLK_1KHZ),.CLK_1HZ(CLK_1HZ));seg_DisplayU2(.CLK_1K(CLK_1KHZ),.RSTN(RSTN),.num_value(time_value),.sel(sel_out),.seg(seg));wireturn,set_add;key_esk#(2)U3(.CLK_1K(CLK_1KHZ),.key_in({TURN,SET_add}),.key_out({turn,set_add}));Dig_clkU6(.CLK_50M(CLK_50M),.CLK_1HZ(CLK_1HZ),.CLK_1K(CLK_1KHZ),.RSTN(RSTN),.selec(turn),.SET_add(set_add),//.SET_sub(SET_sub),.time_value(time_value),.LED(LED));Endmodulemodulekey_esk(inputCLK_1K,input[width-1:0]key_in,output[width-1:0]key_out);parameterwidth=3;reg[width:0]key1,key2,key3;assignkey_out=~(key1|key2|key3);always@(posedgeCLK_1K)beginkey1=key_in;key2=key1;key3=key2;endendmodule
本文标题:基于FPGAverilog数字钟源码
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