基于FPGA的乘法器实现结构分析与仿真

FPGA,(ATR,410073):(FPGA)(DSP),DSP,,FPGA,FPGAXilinxISE4.1i,VHDLVIRELOG:DSP;;FPGA:TN47:A:1002-2279(2004)03-0003-05TheAnalysisandSimulatingforFPGA-BasedMultiplierImplementationStructuresSANJing-hui,CHANGQing(ATR-3Lab,NationalUniversityofDefenseTechnology,Changsha410073,China)Abstract:Theprogressinfieldprogrammablegatearrays(FPGAs)providesnewoptionsforDSPdesignengineers.Andthemultiplicationisoneofthemostimportantoperationsinthefieldofdigitalsignalprocessing(DSP).Hence,inthispaper,thecharacteristicofmultiplicationisanalyzedandsomedifferenttypesofmultiplierstructuresareoffered.Andtheperformanceevaluationandcomparison(areaandspeed)forthesemultiplierimplementationstructureshavebeencarriedoutbyutilizingtheHardDescribeLanguage(VHDLandVIRELOG)andISEsoftwarepackageV4.1ifromXilinx.Keywords:Digitalsignalprocessing(DSP);Multiplier;Fieldprogrammablegatearray(FPGA)1,(DSP)DSP,,DSP(ASICs)(FPGA),FPGAASIC,,,,ASIC,,:,;,FPGA,,,;FPGA,,FPGA;,FPGA,FPGADSP,:FPGADSP,,,(1974-),,,,,:DSPASIC:2003-08-31320046MICROPROCESSORSNo.3Jun.,2004©1994-2009ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.:,,,,,1,,N,2N,881616,N,2N:,N2N,N,N,N2N;,,,N,N:A,B,S,N,C2,S,A[0](,B),NSN,()A[N-1:1]2N,2NNS,NA,N,N,N,,,,,:,23(Booth)(Boothalgorithm):1,3,15(A)89(B),1XB,3Booth,,,,,42004©1994-2009ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.(A;A,:,,),AM,M:1BoothA2NA2N-1Q00001B102B113B:n=1,2,3,......Mö2,A2nA2n,Q+3B,,3B(4B-B),-B,CJ,+4B,,,+B,+4B,:2BoothA2NA2N-1CJN-1QCJN000+00001+B0010+B0011+2B0100+2B0101-B1110-B1111-012Booth2:;Z0=X0ÝY0;CJ0;A2nA2n-1CJ;B[-B],2B,B;N(),Nö2,,,,0B2B-B,(Mö2),N,Nö2,Nö2+1,,,,CJ,,,,,BoothBooth,,4,,,,2564425ns6,3336000001010011100101110111000000000000000000000000000000000000000000000000000001000000000001000010000011000100000101000110000111010000000000010000100000110001000001010001100001110011000000000011000110001001001100001111010010010101100000000000100001000001100010000010100011000011100101000000000101001010001111010100011001011110100011110000000000110001100010010011000011110100100101010111000000000111001110010101011100100011101010110001Xilinx(FPGA),,,,,828+816,?,,4675428240350+30003618675428240350+30003618675428240350+30003618675428240350+300036184,,,,,,553:FPGA©1994-2009ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.()LUT,,33LUT,,LUT,(FPGA)4LUT,,22LUT,,5,6,818,61,2,8716646,7166,,,,,877,,,,,,,88,1:,,6XilinxISE4.1i,VHDLVERILOG,4X444LUT2,8X8164LUT4,62004©1994-2009ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.(slice)(ns)(ns)(ns)(ns)8234.5933.0417.64861.12Booth8355.8665.50911.395556.9754819973.9324.5021.5002.0795.4336.5812410.86626.3248161074194.2284.1382.4912.986.7177.161116.7177.161,,,,()(),FPGA,,,,88,100MHz80ns,,;Booth,;,,,:,,,,,7FPGA,FPGA,,:[1],.CPLDöFPGA[M].:,2002.[2],,.TMS320C600DSPs[M].:,2000.[3]MAAshour3,HISaleh.AnFPGAimplementationguideforsomedifferenttypesofserial-parallelmultiplierstructures[J].MicroelectronicsJournal,2000;31(3):161-168.(2)INTEL0.09Lm,,,,,0.1Lm,,0.1100nm(0.00010.1Lm),,21,CMOS,:;(SOC);,,,,0.09Lm,:[1].211999[M].,1999;(1):2-3.[2].[M].,1998;(3):2-5.[3].[M].,2003;(6):69-74.[4].[M].,2003;31(2):1-3.[5].ULSI[M].,2003;(1):19-20.[6],.[M].,2003;(2):91-92.73:FPGA©1994-2009ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.