3-8译码器的VHDL设计

3-8译码器的VHDL设计1.实体框图2.程序设计正确的程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDECODER38AISPORT(A2,A1,A0,S1,S2,S3:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYDECODER38A;ARCHITECTUREONEOFDECODER38AISSIGNALS:STD_LOGIC_VECTOR(5DOWNTO0);BEGINS=A2&A1&A0&S1&S2&S3;WITHSSELECTY=11111110WHEN000100,11111101WHEN001100,11111011WHEN010100,11110111WHEN011100,11101111WHEN100100,11011111WHEN101100,10111111WHEN110100,01111111WHEN111100,11111111WHENOTHERS;ENDARCHITECTUREONE;3.仿真波形图4.仿真波形分析当S1S2S3=100时，只有当A2A1A0=111时，Y[7]才输出低电平，否则为高电平，当A2A1A0=110时，Y[6]才输出低电平，否则为高电平，当A2A1A0=101时，Y[5]才输出低电平，否则为高电平，Y[4]到Y[0]同理。可见该程序设计的是3-8译码器三、共阳极数码管七段显示译码器的VHDL设计1.实体框图2.程序设计正确的程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDISPLAY_DECODERISPORT(A3,A2,A1,A0:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDENTITYDISPLAY_DECODER;ARCHITECTUREONEOFDISPLAY_DECODERISSIGNALS:STD_LOGIC_VECTOR(3DOWNTO0);BEGINS=A3&A2&A1&A0;WITHSSELECTY=1111110WHEN0000,0110000WHEN0001,1101101WHEN0010,1111001WHEN0011,0110011WHEN0100,1011011WHEN0101,1011111WHEN0110,1110000WHEN0111,1111111WHEN1000,1111011WHEN1001,0000000WHENOTHERS;ENDARCHITECTUREONE;3.仿真波形图4.仿真波形分析由图可知，当A3A2A1A0=0000时，输出Y[6]到Y[0]对应为1111110，即只有g不亮，数码管显示为0，A3A2A1A0=0001时，输出对应为0110000，数码管显示为1，A3A2A1A0=0010时，输出对应为1101101，数码管显示为2，其他同理，当A3A2A1A01001，即大于9，数码管无显示。由此可知，程序设计的是七段显示译码管。