数字系统设计与PLD应用答案

1.7、A÷BABC(余)D(商)8448(1)算法模型NY开始RC←ARB←BRD←0RB=0RC≥RBRC←RC-RBRD←RD+1NERROR结束Y(2)数据处理单元(框图)控制单元MUXRCSUBRBCOMP≥1CTRD8884448ADBC4C2C1C3C1C2C3C4ERRORCRCRRC≥RB82.10、开始WAITSTARTi←AE+1i←i-1启动TEM1FULLFILL=1AG=1TEM1FOR=1EMPTYi=0启动TEM2SPIN=1TEM2NNNNNNYYYYYY2.17、流水线操作结构：TS1=18*100+(256-1)*100=2.73*104(ns)顺序算法结构：TS2=256*18*100=4.608*105(ns)显然流水线操作时间短。（若系统输入数据流的待处理数据元素为m个，每一元素运算共计L段，每段历经时间为Δ，则流水线操作算法结构共需运算时间为：T=L·Δ+(m-1)Δ而顺序算法（或并行算法）结构所需运行时间为：m·L·Δ）2.30、(1).DFF状态编码A—000B—001C—010D—011E—100001101100010---XQ1Q0Q201001101100100---XQ1Q0Q20100110110000---Q1Q0Q201D2D1D0ZZ输出：XSETOUDOUTCOUTBOUTAOUTQQQQQQQQQQQQQQQ012012012012012（2）“一对一”状态分配QQQQQEDCBA43210次态表：NSPS输入条件AAZCXEXBAZCBZCXDBZED-EX激励方程：XZXZZXXZQQDQDQQDQDQQQD43413212014200输出：XSETOUDOUTCOUTBOUTAOUTQQQQQ432103.2、试给出一位全减器的算法描述和数据流描述真值表：xybidbo0000000111010110110110010101001100011111x—被减数y—减数bi—低位向本位的借位d—差bo—本位向高位的借位LIBRARYIEEE;USEIEEE.Std_Logic_1164.ALL;ENTITYfull_subISPORT(x,y,bi:INStd_Logic;d,bo:OUTStd_Logic);ENDfull_sub;算法描述：ARICHITECTUREalg_fsOFfull_subISBIGINPROCESS(x,y,bi)BEGINIF(x=‘0’ANDy=‘0’ANDbi=‘0’ORx=‘1’ANDy=‘0’ANDbi=‘1’ORx=‘1’ANDy=‘1’ANDbi=‘0’)THENbo=‘0';d=‘0’;ELSIF(x=‘1’ANDy=‘0’ANDbi=‘0’)THENbo=‘0';d=‘1’;ELSIF(x=‘0’ANDy=‘1’ANDbi=‘1’)THENbo=‘1';d=‘0’;ELSEbo=‘1';d=‘1’;ENDIF;ENDPROCESSc1;ENDalg_fs;数据流描述：（d=x⊕y⊕bibo=x’y+x’bi+ybi）ARICHITECTUREdataflow_fsOFfull_subISBEGINd=xXORyXORbi;bo=(NOTxANDy)OR(NOTxANDbi)OR(yANDbi);ENDdataflow_ha;3.4、(1).十进制-BCD码编码器，输入、输出均为低电平有效。LIBRARYIEEE;USEIEEE.Std_Logic_1164.ALL;ENTITYencoderISPORT(a:INStd_Logic_Vector(9DOWNTO0)b:OUTStd_Logic_Vector(3DOWNTO0));ENDencoder;ARCHITECTUREbeh_encoderOFencoderISBEGINWITHaSELECTb=“0110”WHEN“0111111111”,“0111”WHEN“1011111111”,“1000”WHEN“1101111111”,“1001”WHEN“1110111111”,“1010”WHEN“1111011111”,“1011”WHEN“1111101111”,“1100”WHEN“1111110111”,“1101”WHEN“1111111011”,“1110”WHEN“1111111101”,“1111”WHEN“1111111110”,“0000”WHENOTHERS;ENDbeh_encoder;补充：优先编码器LIBRARYIEEE;USEIEEE.Std_Logic_1164.ALL;ENTITYencoderISPORT(a:INStd_Logic_Vector(9DOWNTO0)b:OUTStd_Logic_Vector(3DOWNTO0));ENDencoder;ARCHITECTUREbeh_encoderOFencoderISBEGINWITHaSELECTb=“0110”WHEN“0XXXXXXXXX”,“0111”WHEN“10XXXXXXXX”,“1000”WHEN“110XXXXXXX”,“1001”WHEN“1110XXXXXX”,“1010”WHEN“11110XXXXX”,“1011”WHEN“111110XXXX”,“1100”WHEN“1111110XXX”,“1101”WHEN“11111110XX”,“1110”WHEN“111111110X”,“1111”WHEN“1111111110”,“0000”WHENOTHERS;ENDbeh_encoder;(2).时钟RS触发器。1SC11RQSCPRQLIBRARYIEEE;USEIEEE.Std_Logic_1164.ALL;ENTITYclk_rs_ffISPORT(r,s,cp:INStd_Logic;q,nq:BUFFERStd_Logic);ENDclk_rs_ff;ARCHITECTUREbeh_clkrsffOFclk_rs_ffISBEGINASSERTNOT(r=‘1‘ANDs=‘1')REPORTControlerrorSEVERITYError;PROCESS(r,s,cp)BEGINIFcp=‘1’THENq=sOR(NOTrANDq);nq=NOT(sOR(NOTrANDq));ENDIF;ENDPROCESS;ENDbeh_clkrsff;(3).带复位端、置位端、延迟为15ns的响应CP下降沿的JK触发器。S1JC11KRQQSCPRJKLIBRARYIEEE;USEIEEE.Std_Logic_1164.ALL;ENTITYjk_ffISGENERIC(tpd:Time:=15ns);FORT(r,s,j,k,cp:INStd_Logic;q,nq:BUFFEERStd_Logic);ENDjk_ff;ARCHITECTUREbeh_jkffOFjk_ffISBEGINASSERTNOT(r='0‘ANDs='0')REPORTControlerrorSEVERITYError;PROCESS(r,s,cp)BEGINIFr=‘0’THENq=‘0’AFTERtpd;nq=‘1’AFTERtpd;ELSIFs=‘0’THENq=‘1’AFTERtpd;nq=‘0’AFTERtpd;ELSIF(cp’EventANDcp=‘0‘)THENq=jANDnqORNOTkANDqAFTERtpd;nq=NOT(jANDnqORNOTkANDq)AFTERtpd;ENDIF;ENDPROCESS;ENDbeh_jkff;(4).集成计数器74161。LIBRARYIEEE;USEIEEE.Std_Logic_1164.ALL;USEIEEE.Std_Logic_Unsigned.ALL;ENTITYcounter16ISPORT(cr,ld,cp,ctt,ctp:INStd_Logic;d:INStd_Logic_Vector(3DOWNTO0);q:BUFFERStd_Logic_Vector(3DOWNTO0);co:OUTBit);ENDcounter16;ARCHITECTUREbehav_ctr16OFcounter16ISBEGINPROCESS(cr,cp)BEGINIFcr=‘0’THENq=“0000”;ELSIF(cp’EventANDcp=‘1’)THENIFld=‘0’THENq=d;ELSIF(ctt=‘1’ANDctp=‘1’)THENIFq=“1111”THENq=“0000”;ELSEq=q+“0001”;ENDIF;ENDIF;ENDIF;ENDPROCESS;co=‘1’WHEN(q=“1111”ANDctt=‘1’)ELSE‘0’;ENDbeh_ctr16;(5).集成移位寄存器74194。LIBRARYIEEE;USEIEEE.Std_Logic_1164.ALL;ENTITYsrgISPORT(cr,cp:INStd_Logic;d:INStd_Logic_Vector(3DOWNTO0);sl,sr:INStd_Logic;m:INStd_Logic_Vector(1DOWNTO0);q:BUFFERStd_Logic_Vector(3DOWNTO0));ENDsrg;ARCHITECTUREbehav_srgOFsrgISBEGINPROCESS(cr,cp)BEGINIFcr=‘0'THENq=“0000”;--异步复位ELSIF(cp’EventANDcp=‘1’)THENCASEmISWHEN01=q=sr&q(3DOWNTO1);--右移WHEN10=q=q(2DOWNTO0)&sl;--左移WHEN11=q=d;--并行输入(同步预置)WHENOTHERS=NULL;--空操作，即保持ENDCASE;ENDIF;ENDPROCESS;ENDbehav_srg;3.6、(2).由D触发器构成的异步二进制模8计数器1DC11DC11DC1CPQ0Q1Q2异步2k进制计数器的电路结构计数规律触发方式上升沿下降沿加法QiCPi1QiCPi1减法QiCPi1QiCPi1LIBRARYIEEE;USEIEEE.Std_Logic_1164.ALL;ENTITYasyn_ctr8ISPORT(cp:INBit;q:BUFFERStd_Logic_Vector(2DOWNTO0));ENDctr8;ARCHITECTUREstruct_ctr8OFasyn_ctr8ISCOMPONENTd_ffPORT(clk,d:INStd_Logic;q,nq:OUTStd_Logic);ENDCOMPONENT;SIGNALnq0,nq1,nq2:Std_Logic;BEGINff0:d_ffPORTMAP(cp,nq0,q(0),nq0);ff1:d_ffPORTMAP(q(0),nq1,q(1),nq1);ff2:d_ffPORTMAP(q(1),nq2,q(2),nq2);ENDstruct_ctr8;4.3、一位全减器：输入为x(被减数)、y(减数)、bi(低位借位)、d(差)和bo(本位向高位的借位)(1).PROM实现：xybidboXybi(2).PLA实现：001101100101010ybix01d1001101100110010ybix01bo111111xybidboXybi4.10、QQQQDQQQQQQZQQQQDQQQQQQQQZQQQQDQnnnnnnnnnnnnnnn12012120121220102111012011210212010状态转换图：000/01001/11011/00111/11110/10100/01010/00101/00Q2Q1Q0/Z2Z1