EDA实训资料1·全加器&全减器程序

给出1位全减器的VHDL描述。首先设计1位半减器，然后用例化语句将它们连接起来底层文件半减器（h_suber）程序设计：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYh_suberISPORT(x,y:INSTD_LOGIC;diff,s_out:OUTSTD_LOGIC);ENDENTITYh_suber;ARCHITECTUREfh1OFh_suberISSIGNALabc:STD_LOGIC_VECTOR(1DOWNTO0);BEGINabc=x&y;PROCESS(abc)BEGINCASEabcISWHEN00=diff='0';s_out='0';WHEN01=diff='1';s_out='1';WHEN10=diff='1';s_out='0';WHEN11=diff='0';s_out='0';WHENOTHER=NULL;ENDCASE;ENDPROCESS;ENDARCHITECTUREfh1;底层文件或门（or2a）程序设计：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYor2aISPORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDENTITYor2a;ARCHITECTUREoneOFor2aISBEGINC=aORb;ENDARCHITECTUREone;根据连接图，顶层文件全减器（f_suber）程序设计：defsub_outxinyinsub_indiffoutxdiffys_outxdiffys_outLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYf_suberISPORT(xin,yin,sub_in:INSTD_LOGIC;diffout,sub_out:OUTSTD_LOGIC);ENDENTITYf_suber;ARCHITECTUREfd1OFf_suberISCOMPONENTh_suberPORT(x,y:INSTD_LOGIC;diff,s_out:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTor2aPORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALd,e,f:STD_LOGIC;BEGINu1:h_suberPORTMAP(x=xin,y=yin,diff=d,s_out=e);u2:h_suberPORTMAP(x=d,y=sub_in,diff=diffout,s_out=f);u3:or2aPORTMAP(a=f,b=e,c=sub_out);ENDARCHITECTUREfd1;全加器程序参照自动化同学课本，原理与全减器类似。