多功能数字钟课程设计VHDL代码书上程序改

libraryieee;useieee.std_logic_1164.all;entityclockisport(clk1hz:instd_logic;--1hz脉冲--clk100:instd_logic;--100hz脉冲--weekclk:instd_logic;--星期调整脉冲--start_stop:instd_logic;--秒表启动/停止控制--reset:instd_logic;--秒表复位--adclk:instd_logic;--校时脉冲--setselect:instd_logic;--调整位选择脉冲--mode:instd_logic;--功能选择脉冲--showdate:instd_logic;--日期显示--dis:outstd_logic_vector(23downto0);--显示输出--glisten:outstd_logic_vector(5downto0);--闪烁指示--weekout:outstd_logic_vector(3downto0);--星期输出--qh:outstd_logic--整点报时--);endclock;architecturearchofclockiscomponentadjustport(adclk:instd_logic;data_in:outstd_logic_vector(7downto0));endcomponent;componentcontrolport(setclk:instd_logic;setlap:outstd_logic_vector(1downto0);mode:instd_logic;module:outstd_logic_vector(2downto0));endcomponent;componentweekcounterport(clk:instd_logic;clk2:instd_logic;q:outstd_logic_vector(3downto0));endcomponent;componentstopwatchport(clk:instd_logic;reset:instd_logic;start_stop:instd_logic;centsec:outstd_logic_vector(7downto0);sec:outstd_logic_vector(7downto0);min:outstd_logic_vector(7downto0));endcomponent;componenth_m_s_countport(clk:instd_logic;set:instd_logic;setlap:instd_logic_vector(1downto0);d:instd_logic_vector(7downto0);sec:outstd_logic_vector(7downto0);min:outstd_logic_vector(7downto0);hour:outstd_logic_vector(7downto0);qh:outstd_logic;qc:outstd_logic);endcomponent;componenty_m_d_countport(clk:instd_logic;set:instd_logic;setlap:instd_logic_vector(1downto0);data_in:instd_logic_vector(7downto0);day:outstd_logic_vector(7downto0);month:outstd_logic_vector(7downto0);year:outstd_logic_vector(7downto0));endcomponent;componentdisplayport(module:instd_logic_vector(2downto0);showdate:instd_logic;clk:instd_logic;setlap:instd_logic_vector(1downto0);watch:instd_logic_vector(23downto0);time:instd_logic_vector(23downto0);date:instd_logic_vector(23downto0);dis:outstd_logic_vector(23downto0);glisten:outstd_logic_vector(5downto0));endcomponent;signaldata_in,mcentsec,msec,mmin,ssec,smin,shour,sdate,smonth,syear:std_logic_vector(7downto0);signalsetlap:std_logic_vector(1downto0);signalmodule:std_logic_vector(2downto0);signalqc:std_logic;signalwatch,time,date:std_logic_vector(23downto0);beginu1:adjustportmap(adclk,data_in);u2:controlportmap(setselect,setlap,mode,module);u3:stopwatchportmap(clk100,reset,start_stop,mcentsec,msec,mmin);u4:h_m_s_countportmap(clk1hz,module(1),setlap,data_in,ssec,smin,shour,qh,qc);u5:y_m_d_countportmap(qc,module(2),setlap,data_in,sdate,smonth,syear);u6:displayportmap(module,showdate,clk1hz,setlap,watch,time,date,dis,glisten);u7:weekcounterportmap(qc,weekclk,weekout);watch=mmin&msec&mcentsec;time=shour&smin&ssec;date=syear&smonth&sdate;endarch;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityadjustisport(adclk:instd_logic;data_in:outstd_logic_vector(7downto0));endadjust;architecturearchofadjustissignaltemp2,temp1:std_logic_vector(3downto0);beginprocess(adclk)beginifrising_edge(adclk)theniftemp1=1001thentemp2=temp2+'1';temp1=0000;elsetemp1=temp1+'1';endif;iftemp2=1001andtemp1=1001thentemp1=0000;temp2=0000;endif;endif;data_in=temp2&temp1;endprocess;endarch;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycontrolisport(setclk:instd_logic;--调整脉冲--setlap:outstd_logic_vector(1downto0);--调整位选择脉冲--mode:instd_logic;--功能选择脉冲--module:outstd_logic_vector(2downto0)--功能输出--);endcontrol;architecturearchofcontrolissignalssetlap:std_logic_vector(1downto0);signals:std_logic_vector(3downto0);beginprocess(mode,setclk)beginifmode='1'thenssetlap=00;elsifrising_edge(setclk)thenifssetlap=10thenssetlap=00;elsessetlap=ssetlap+'1';endif;endif;endprocess;setlap=ssetlap;process(mode)beginifrising_edge(mode)thencasesiswhen0001=s=0010;when0010=s=0100;when0100=s=1000;when1000=s=0001;whenothers=s=0010;endcase;endif;endprocess;module=s(3downto1);endarch;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitycounter60isport(clk:instd_logic;--计数脉冲--clr:instd_logic;--复位--q:outstd_logic_vector(7downto0);--计数值--qc:outstd_logic--进位输出--);endcounter60;architecturearchofcounter60issignaltemp1,temp2:std_logic_vector(3downto0);beginprocess(clr,clk)beginifclr='1'thentemp1=0000;temp2=0000;elsifrising_edge(clk)theniftemp1=1001thentemp2=temp2+'1';temp1=0000;elsetemp1=temp1+'1';endif;iftemp2=0101andtemp1=1001thentemp1=0000;temp2=0000;qc='1';elseqc='0';endif;endif;q=temp2&temp1;endprocess;endarch;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitycounter99isport(clk:instd_logic;--100vhz计数脉冲--en:instd_logic;--计数使能--clr:instd_logic;--复位--q:outstd_logic_vector(7downto0);--计数值--qc:outstd_logic--进位--);endcounter99;architecturearchofcounter99issignaltemp1,temp2:std_logic_vector(3downto0);beginprocess(clr,clk)beginifclr='1'thentemp1=0000;temp2=0000;elsifrising_edge(clk)thenifen='1'theniftemp1=1001thentemp2=temp2+'1';temp1=0000;elsetemp1=temp1+'1';endif;iftemp2=1001andtemp1=1001thentemp1=0000;temp2