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[19.VGACONNECTOR][15.DMILAI][11.H3SOCKET][10.H3SOCKET][9.H3SOCKET][59.USBBACKPANNEL][108.VCOREVREG][112.TESTSITECAPSANDSTICHINGCAPS][114.HALFLENGTHMINIPCI-E][70.AUDIODCPL,CIRCUITS&JACKSENSE][17.DIMMVREFS&THERMALSENSOR][3.SEQUENCINGDIAGRAM]2011[97.BLANKPAGE][98.VREG:DECOUPLINGANDSTITCHING][99.PORT80DISPLAY][100.MULTIBIOSSUPPORTANDECSTUFFING][117.BOMSTUFFINGINFO][116.PCHXDP][115.MINIPCIEVREG][4.CLOCKDISTRIBUTION][96.VREG:USB/5VDUALPCH/NCH][20.PCIEXPRESSX16(0_TO_15]COMPONENT/FUNCTION-12V[2.BLOCKDIAGRAM][1.INDEX][16.DIMMVREFS][14.MCPTERMINATION][111.CPUDECOUPLING][5.GPIO,IRQ,IDSELMAP][6.H3SOCKET][7.H3SOCKET][13.H3SOCKET][113.PRIMARYXDP]+12V[95.VREG:3P3_STBY][43.PCH6]PAGE#VCC[46.HDMI]DESIGN[45.DISPLAYDATAESDDIODES][18.NFC][42.PCH10][44.PCH8][8.H3SOCKET][12.H3SOCKET]TAPE-OUT:WWXX-2011POWERSYMBOLSUSED:[105.EC:SERIALPORT][110.VCOREVREG][109.VCOREVREG][107.VCOREVREG][106.VREG:V_1P5_PCH][81.PWRGOODLOGIC][85.SERIALFLASHSECONDARY][86.FANCIRCUITRY][57.USBFPHDR4][53.SATACONNECTORS][49.GPIOTERMINATION&RSTSTRAPS][56.USBFPHDR3][55.USBFPHDR2][54.USBFPHDR1][51.PCHDECOUPLING][52.PCHSTRAPS][76.AUDIOVREG][69.AUDIOCODEC][73.AUDIOJACK(BLACKORANGE][75.AUDIOMICBIAS&SPIDIFHDR][78.RESUMERESETLOGIC][84.SERIALFLASHPRIMARY][80.PWRLEDLOGIC][79.SPITPM][77.LPC_BUS][74.AUDIOFPHEADERS&HDAHEADER][72.AUDIOJACKS][71.AUDIOSPDIF][68.LAN:MAGJACK][67.LANCONTROLLER][66.MSATA][65.EDP][64.STDFRONTPANELHDR][63.PCHTERMINATION][62.BLANKPAGE][61.USB3ESDDIODES][60.USBBACKPANNEL][58.USBBACKPANEL/DPSTACK2]COMPONENT/FUNCTIONCOMPONENT/FUNCTION[50.PCHPINSTRAPS][101.BLANKPAGE][102.MICROCONTROLLER1OF][103.MICROCONTROLLER2OF3][104.MICROCONTROLLER3OF3][21.PCIEXPRESSX16COUPLING][22.PCIEXPRESSX1#1][23.PCIEEXPRESSX1#2][24.PCIEXPRESSX1#3][25.PCIEX4SLOT][26.CONNDDR3,CHADIMM0][27.CONNDDR3,CHADIMM1][28.CONNDDR3,CHBDIMM0][29.CONNDDR3,CHBDIMM1][30.DSWSEQUENCING][41.PCH9][40.PCH7][39.PCH5][34.CK505PAGE3OF3][33.BLANKPAGE][38.PCH4][37.PCH3][36.PCH2][47.HDMI][48.HDMI_DISPLAYPORT]VCC3HADDOCKCREEK_CDB[PAGE_TITLE=INDEX]FAB1[83.SPIPROGCIRCUIT][82.PCIERESETLOGIC][32.DSWCIRCUIT][31.DSW5V_DUAL][94.3P3AUX&LAN/EPW][93.VREG:V_1P05_PCH][92.VREG:V_1P05_ME][91.VREG:V_SM_VTT][90.VREG:V_SM][89.POWER-CONN,BATTERY][88.POWERMAP][87.MTGHOLES/LABELS][35.PCH1]MonApr1613:57:332012CR-1:@HC_CDB_MPI_LIB.HC_CDB_MPI(SCH_1):PAGE1HADDOCKCREEK_CDBCHK_BY_DATEPB_NUMBERCHK_BYDOCUMENT_NUMBERENGR_APVDhc_cdb_mpi.sch_1.11.01/117zlowENGR_APVD_DATEDRN_BY_DATEBOM_RELEASE_DATEREV=1P00BOM_RELEASE_DATE4.*SUFFIXINDICATESACTIVELOWSIGNAL.DRN_BY3.VCC=+5VUNLESSOTHERWISESPECIFIED.SIGNATUREDOCUMENT_NUMBERNOTES:BPAGEDRAWINGDATEDATEAPVDCHKDATEREVISIONSDFTDESCRIPTIONREVSENGR_APVDDATE3065BOWERSAVE95051SANTACLARA,CA56287541DDCB87CAA16243REVPAGEB32.RESISTORSAREINOHMSUNLESSOTHERWISESPECIFIED.CUSTOMTEXTB-PAGECHK_BYITEMSSHOWNASOPTIONALINTHESCHEMATIC.PLEASEREFERTOSPECIFICPRODUCTPBAEPLFOR1.THISSCHEMATICDOCUMENTSTHEGENERICPRODUCTWITHALLPOSSIBLECONFIGURATIONS.CONFIDENTIALINTELTITLEintelPB_NUMBER6.THISDOCUMENTALSOEXISTSONELECTRONICMEDIA.5.\ISUFFIXINDICATESSIGNALEXITSHIERARCHICALBLOCK.REVDESCRIPTIONDFTDATEREVISIONSCHKDATEAPVDDATE[PAGE_TITLE=BLOCKDIAGRAM]MonApr1613:57:332012CR-2:@HC_CDB_MPI_LIB.HC_CDB_MPI(SCH_1):PAGE22hc_cdb_mpi.sch_1.2DOCUMENT_NUMBER1.0REVDATEMODULEREVDETAILSMODULENAME2CUSTOMTEXTBPAGE1CONFIDENTIALINTEL6PAGEREV3426ABC78BCDD1345785DOCUMENT_NUMBERBPAGEDRAWINGA[PAGE_TITLE=SEQUENCINGDIAGRAM]MonApr1613:57:332012CR-3:@HC_CDB_MPI_LIB.HC_CDB_MPI(SCH_1):PAGE33hc_cdb_mpi.sch_1.3DOCUMENT_NUMBER1.0REVDATEMODULEREVDETAILSMODULENAME2CUSTOMTEXTBPAGE1CONFIDENTIALINTEL6PAGEREV3426ABC78BCDD1345785DOCUMENT_NUMBERBPAGEDRAWINGA[PAGE_TITLE=CLOCKDISTRIBUTION]PCHPLATFORMCLOCKMonApr1613:57:332012CR-4:@HC_CDB_MPI_LIB.HC_CDB_MPI(SCH_1):PAGE44hc_cdb_mpi.sch_1.4DOCUMENT_NUMBER1.0REVDATEMODULEREVDETAILSMODULENAME2CUSTOMTEXTBPAGE1CONFIDENTIALINTEL6PAGEREV3426ABC78BCDD1345785DOCUMENT_NUMBERBPAGEDRAWINGAGP37COREPCH_GP37INNOANOA,EMPTYPDAND1KTOVCC3GP36COREPCH_GP36INNOANOA,EMPTYPDAND1KTOVCC3GP35CORE2X4_POWER_DETECTINNOANOA&POWERCONN---GP34COREPCH_GP34IN10KPUTOVCC3,10KPDGP32COREPCH_GP32OUT10KEMPTYPUTOVCC3,10KPDGP31DSWPCH_GP31OUT10KPUTOV_3P3_A,NCGP28RESUMEPCH_GP28IN1KPUTO3P3_STBYGP27DSWLANWAKE_NOUT4.7KPUTO3P3_LAN,TOLANGP25RESUMEGP25_PDIN10KTOGNDGP22COREPCH_CONFIG_JUMPERIN4.7KPD,TO1X3HDRGP20COREPCH_SMI_NNATIVE10KPUTOVCC3,10KPDEMPTY,NOAGP18COREPCH_GP18INNOA,10KTOGNDGP14RESUMEIO_PME_NIN10KPUTO3P3STBYGP12DSWLAN_DISABLE_NNATIVE10KPUTO3P3STBY,LANGP10RESUMEUSB_OC6_R_NNATIVEOC#&NOAGP8RESUMEIGC_EN_N/OC_STRAPIN/OUT1KTOHDRTOGND,NOAGP6COREPCH_GP6IN10KPUVCC3,10KTOGNDGP4COREEXTTS_SNI_DRV0_PCHIN8.2KPUVCC3,MEMORYTHERMALSENSINGINTERFACEGP2CORETEST_SETUP_MENUIN10KPUTOVCC3,1X2HDRPDTOGNDGP49COREPCH_GP49INNOANOA,10KOPTOVCC3&GNDGP50COREPCIEX1_SLOT5_PRSNT2_NIN8.2KPUTOVCC3,TOSLOT5GP51COREPCH_GP51NATIVE1KPDTOGNDGP52COREPCIEX1_SLOT4_PRSNT2_NIN8.2KPUVCC3,TOSLOT4GP53COREPCH_GP53IN1KPDTOGNDGP54COREPCIEX1_SLOT6_PRSNT2_NIN8.2KPUTOVCC3,TOSLOT6[PAGE_TITLE=GPIO,IRQ,IDSELMAP]GP1COREPCH_GP1IN10KPUVCC3,10KTOGNDOPTION---GP5COREEXTTS_SNI_DRV1_PCHIN8.2KPUVCC3,MEMORYTHERMALSENSINGIN
本文标题:Intel主板公版线路原理图.
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