ds_nios2_3c25_lcd电子信息外文资料翻译原件

©March2009AlteraCorporationNiosII3C25MicroprocessorwithLCDControllerDataSheetDS-01003-1.1©March2009NiosII3C25MicroprocessorwithLCDControllerDataSheetIntroductionThisdatasheetdescribesasingleinstanceofaNios®II-basedprocessorsystemwithabuilt-inLCDcontrollertargetedforanAltera®Cyclone®III3C25F324FPGAontheAlteraNiosIIEmbeddedEvaluationKit,CycloneIIIEdition.TheNiosII3C25MicroprocessorwithLCDControllerisacompletesystem-on-a-programmable-chip(SOPC)solutionthatincorporatesarichsetofsystemperipheralsandstandardinterfacesforawiderangeofembeddedapplicationsinvolvingvideoprocessingandLCDtouchpanelcontrol.ThekeybenefitofimplementingaprocessorsysteminanFPGAisthatyoucancustomizeyoursystemusingintellectualproperty(IP)cores,customlogic,andhardwareaccelerationtooptimizetoyourtargetapplication.Nearlyeveryfeatureinthesystemisavailableforyoutoconfigure,customize,duplicate,orremoveeasily.YoucanfurtherenhanceyoursystembyaddingadditionalIPtotheCycloneIII3C25device,oryoucanremoveIPorselectoptionsthatreducelogicutilizationallowingyoutoporttoasmallerdevicetoreducecost.1AlthoughthisdatasheetdescribesasystemtargetedfortheCycloneIII3C25FPGAdevice,thedatasheetalsoshowsyouhowtoconfiguretheprocessorsystemforanotherAlteraFPGAdeviceandhardwareplatformofyourchoice.FeaturesThefollowinglistsummarizesthemainfeaturesoftheNiosII3C25microprocessorwithLCDcontroller.TargetHardwareBoard■AlteraNiosIIEmbeddedEvaluationKit,CycloneIIIEditionDevice■Systemname:cycloneIII_3c25_niosII_video■Family:CycloneIII■Device:3C25F324■Totallogicelements(LE)used:22,875/24,624(93%)■Totalpinsused:167/216(77%)■Totalmemoryused:163,270/608,256(27%)Processor■NiosII/fprocessorcore■Nominalmetrics:113DMIPSat100MHz,1,400–1,800LEs,MMU/MPUoptiondisabled■4-KByteinstructioncache,2-KBytedatacachePage2IntroductionNiosII3C25MicroprocessorwithLCDControllerDataSheet©March2009AlteraCorporation■JTAGdebugmodulefordownloadingsoftware,300–400LEsMemoryInterfaces■Commonflashinterface(CFI)flashmemory■16MBytes■HighperformanceDDRSDRAMmemory■Nominalfrequency:133MHz,16bits,32MBytes■SD/MMCcardserialperipheralinterface(SPI)■20-MHzSPIinterfaceclockfrequency■Supportsupto1-GbitSDcardmemory■SynchronousSRAMmemory■1MByteCommunicationInterfaces■EthernetMAC10/100/1000BaseT■IntegratedinreceiveandtransmitFIFO512×32bitseach■Mediaindependentinterface(MII)/gigabitmediaindependentinterface(GMII)support■32-bittransmitandreceivescattergatherdirectmemoryaccess(SG-DMA)channels■JTAGUARTwithintegratedreadandwriteFIFO■UARTforRS-232serialcommunication■115,200baudrate,noparity,8databits,1stopbit■2-wireinterface■ImplementedusinggeneralpurposePIOs■DedicatedtoLCDcontrollerinterfaceVideoSubsystem■IntegratedLCDcontrollerIP■Configuredto800×480resolution■InterfaceforLCDcontrolusing2-wireinterface■ImplementedusinggeneralpurposePIOs■IntegratedtouchpanelcontrollerIP■InterfacestoLCDusing3-wireSPI■Mastermode8bitdataregister,32KHzDescriptionPage3©March2009AlteraCorporationNiosII3C25MicroprocessorwithLCDControllerDataSheet■Videopipeline■Streamingvideodatapath■Videoframebuffer■RGBSyncgenerationIP■128-bytedualclockFIFOSystemPeripherals■Timers/counters■Systemclocktimer■32-bitcountersize,10-mstime-outperiod■Highresolutiontimer■32-bitcountersize,10-µstime-outperiod■Performancecounter■1simultaneousmeasuredsection■4buttonPIOs(inputonly)■2LEDPIOs(outputonly)■SystemID■CycloneIIIremoteupdatecontrollerconfigurationperipheralDescriptionTheNiosII3C25microprocessorwithLCDcontrollerincorporatesaNiosIIprocessor,LCDcontroller,memories,avideopipeline,andmoreinasingleCycloneIII3C25FPGA.Youcanconfigurenearlyeveryaspectoftheprocessorsystemtosuityourapplicationrequirements.YoucanconfiguretheNiosIIprocessorasoneoffollowingcores:■Asize-optimizedeconomy(/e)core■Aperformance-optimumfast(/f)core■Anoptimumsize-to-performancestandard(/s)coreInaddition,thefastcorecomeswithoptionstoincludeamemorymanagementunit(MMU)aswellasvariouspreciseexceptionsandmemoryprotectionfeatures.TheNiosIIprocessorsupportscustominstructionsallowingyoutoimplementsoftwarefunctionsinhardwaretoincreasesystemperformance.YoucanconfiguretheJTAGdebugmoduletosupporthardwarebreakpoints,datatriggers,andinstructionanddataon-chipandoff-chiptrace.ThemicroprocessorsupportsanLCDcolortouchpanelbyintegratingtheLCDcontrollerhardware,whichhasbeenimplementedaspartofavideopipeline.Thevideopipelineisfullylogicbased,composedofIPcoresyoucanmodifytosuitanyresolutionoraspectratio.Page4DescriptionNiosII3C25MicroprocessorwithLCDControllerDataSheet©March2009AlteraCorporationADDRSDRAMmemoryinterfaceholdsthevideobuffer.A1-MByteSSRAMmemoryisavailableforprocessorprogramcode.Forcodelargerthan1MByte,theDDRSDRAMmemorycanalsoholdprocessorprogramcode.User-selectableSRAMmemory(on-chip)holdstheDMAdescriptors.ACFIflashcontrollersupportsflashmemorytostoreapplicationcodeandFPGAconfigurationdata.ThemicroprocessorintegratesanSD/MMCcontrollerthatisSDcardcompliant.Thesystemalsoincludesa10/100/1000EthernetMACwithSG-DMAchannelsfornetworkaccess.Figure1showsthefunctionalblocksoftheNiosII3C25microprocessorwithLCDcontrollersystem.Table1liststhepi