数模混合电路设计

MixedAnalogandDigitalIntegratedCircuitDesignê·Ü8¤´[e-mail]‰EŒÆ2009–2010ÆcþÆÏLi,Qiang(UESTC-SCIE)MixedAnalogandDigitalICDesignLecture10,Fall20091/66AdministrativesAdministrativeIssuesLecturetimechangeDec.17,5–[e-mail])Cancelled/PostponedDec.22,5–[e-mail])Cancelpossibly,TBDDec.29,5–[e-mail])Cancelpossibly,TBDProjecttopics10-b200-MS/sADC14-b20-MS/sADC12-b200-MS/sDACExamination15students/groupProjectpresentation,week20(Jan.12&14,2010)Slidestobesubmitted1dayearlier(12:59pm@Jan.11&13)Finalreport,40+pages,due12:59pm@Jan.15,2010Email:[e-mail],Qiang(UESTC-SCIE)MixedAnalogandDigitalICDesignLecture10,Fall20092/66AdministrativesReport/PresentationOutlineIntroductionsystemapplicationkeypoint/noveltyofthedesignLiteratureSurvey(JSSC/ISSCConly)state-of-the-artperformancemetricspopular/mainstreamtechniques(2-3)who?when?how?anytrade-off?mustwith10+references!SystemDesignarchitecture&considerationsblockspecificationBlockDesigndesignconsideration&issuescircuittopologySimulationResultConclusionReferencesLi,Qiang(UESTC-SCIE)MixedAnalogandDigitalICDesignLecture10,Fall20093/66ReviewofLastLectureEECS247-Lecture16DACDesign(continued)-IntroductiontoADCs©2008H.K.Page11•Notethateachcurrentcellhasitsclockedlatchandclocksignallaidouttobeclosetoitsswitchtoensuresimultaneousswitchingofcurrentsources•SpecialattentionpaidtothefinallatchtohavethecrosspointofthecomplementaryswitchcontrolsignalsuchthatthetwoswitchesarenotbothturnedoffduringtransitionEECS247-Lecture16DACDesign(continued)-IntroductiontoADCs©2008H.K.Page12•MeasuredDNL/INLwithcurrentassociatedwiththecurrentcellsasvariableDNL/INL[LSB]IFull-Scale[mA]Li,Qiang(UESTC-SCIE)MixedAnalogandDigitalICDesignLecture10,Fall20094/66ReviewofLastLecture...inLastLectureQuestion:WhyDNL/INLisbetterwithlargercurrent?Ids=120CoxWL(VGSVth)2I)(VGSVth)WLfabricated/fixeddIdId=2VGSVthhdW=LW=L+dVthiLargerVdsat,betterDNL/INL/Li,Qiang(UESTC-SCIE)MixedAnalogandDigitalICDesignLecture10,Fall20095/66Analog-to-DigitalConvertersEECS247-Lecture16DACDesign(continued)-IntroductiontoADCs©2008H.K.Page27SummaryD/AConverter•D/Aarchitecture–Unitelement–complexityproportionalto2B-excellentDNL–Binaryweighted-complexityproportionaltoB-poorDNL–Segmented-unitelementMSB(B1)+binaryweightedLSB(B2)ÆComplexityproportional((2B1-1)+B2)-DNLcompromisebetweenthetwo•Staticperformance–Componentmatching•Dynamicperformance–Timeconstants,Glitches•DACimprovementtechniques–Symmetricalswitchingratherthansequentialswitching–Currentsourceselfcalibration–Dynamicelementmatching•Dependingontheapplication,reconstructionfiltermaybeneededEECS247-Lecture16DACDesign(continued)-IntroductiontoADCs©2008H.K.Page28WhatNext?•ADCConverters:–Needtobuildcircuitsthatsample“–NeedtobuildcircuitsforamplitudequantizationAnalogPostprocessingD/AConversionDSPA/DConversionAnalogPreprocessingAnalogInputAnalogOutput000...001...110Anti-AliasingFilterSampling+QuantizationBitstoStaircaseReconstructionFilterLi,Qiang(UESTC-SCIE)MixedAnalogandDigitalICDesignLecture10,Fall20096/66Analog-to-DigitalConvertersEECS247-Lecture16DACDesign(continued)-IntroductiontoADCs©2008H.K.Page29Analog-to-DigitalConverters•Twocategories:–NyquistrateADCsÆfsigmax~0.5xfsampling•Maximumachievablesignalbandwidthhighercomparedtooversampledtype•Resolutionlimitedtomax.12-14bits–OversampledADCsÆfsigmax0.5xfsampling•Maximumachievablesignalbandwidthsignificantlylowercomparedtonyquist•Maximumachievableresolutionhigh(18to20bits!)EECS247-Lecture16DACDesign(continued)-IntroductiontoADCs©2008H.K.Page30MOSSamplingCircuitsLi,Qiang(UESTC-SCIE)MixedAnalogandDigitalICDesignLecture10,Fall20097/66Analog-to-DigitalConvertersMOSSamplingCircuitsEECS247-Lecture16DACDesign(continued)-IntroductiontoADCs©2008H.K.Page29Analog-to-DigitalConverters•Twocategories:–NyquistrateADCsÆfsigmax~0.5xfsampling•Maximumachievablesignalbandwidthhighercomparedtooversampledtype•Resolutionlimitedtomax.12-14bits–OversampledADCsÆfsigmax0.5xfsampling•Maximumachievablesignalbandwidthsignificantlylowercomparedtonyquist•Maximumachievableresolutionhigh(18to20bits!)EECS247-Lecture16DACDesign(continued)-IntroductiontoADCs©2008H.K.Page30MOSSamplingCircuitsLi,Qiang(UESTC-SCIE)MixedAnalogandDigitalICDesignLecture10,Fall20098/66Analog-to-DigitalConvertersMOSSamplingCircuitsEECS247-Lecture16DACDesign(continued)-IntroductiontoADCs©2008H.K.Page31IdealSampling•Inanidealworld,zeroresistancesamplingswitcheswouldcloseforthebriefestinstanttosampleacontinuousvoltagevINontothecapacitorCÆOutputDirac-likepulseswithamplitudeequaltoVINatthetimeofsampling•Inpracticenotrealizable!vINvOUTCS1φ1φ1T=1/fSEECS247-Lecture16DACDesign(continued)-IntroductiontoADCs©2008H.K.Page32IdealTrack&HoldSamplingvINvOUTCS1φ1•Vouttracksinputfor½clockcyclewhenswitchisclosed•AcquiresexactvalueofVinattheinstanttheswitchopens•TrackandHold(T/H)(oftencalledSample&Hold!)φ1T=1/fSLi,Qiang(UESTC-SCIE)MixedAnalogandDigitalICDesignLecture10,Fall20099/66Analog-to-DigitalConvertersMOSSamplingCircuitsEECS247-Lecture16DACDesign(continued)-IntroductiontoADCs©2008H.K.Page31Id