VHDL基本逻辑电路设计

第6章基本逻辑电路设计6.1组合逻辑电路设计6.2时序逻辑电路设计6.3存储器习题第6章基本逻辑电路设计6.1组合逻辑电路设计6.1.1简单门电路1.2输入“与非”门LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYnand2ISPORT(a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDnand2;ARCHITECTUREnand2_rtlOFnand2ISBEGINy=aNANDb;--NOT(aANDb)ENDnand2_rtl;ARCHITECTUREnand2_behaveOFnand2ISBEGINPROCESS(a,b)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=a&b;CASEcombISWHEN“00”=y=‘1’;WHEN“01”=y=‘1’;WHEN“10”=y=‘1’;WHEN“11”=y=‘0’;WHENOTHERS=y=‘X’;ENDCASE;ENDPROCESS;ENDnand2_behave;数据流描述行为描述第6章基本逻辑电路设计2.2输入“或非”门LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYnor2ISPORT(a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDnor2;ARCHITECTUREnor2_rtlOFnor2ISBEGINy=aNORb;--NOT(aORb)ENDnor2_rtl;ARCHITECTUREnor2_behaveOFnand2ISBEGINPROCESS(a,b)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=a&b;CASEcombISWHEN“00”=y=‘1’;WHEN“01”=y=‘0’;WHEN“10”=y=‘0’;WHEN“11”=y=‘0’;WHENOTHERS=y=‘X’;ENDCASE;ENDPROCESS;ENDnor2_behave;数据流描述行为描述第6章基本逻辑电路设计3.反相器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYinverterISPORT(a:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDinverter;ARCHITECTUREinverter_rtlOFinverterISBEGINy=NOTa;ENDinverter_rtl;ARCHITECTUREinverter_behaveOFinverterISBEGINPROCESS(a)BEGINIF(a=‘1’)THENy=‘0’;ELSEy=‘1’;ENDIF;ENDPROCESS;ENDinverter_behave;数据流描述行为描述第6章基本逻辑电路设计4.2输入“异或”门LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYxor2ISPORT(a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDxor2;ARCHITECTURExor2_rtlOFxor2ISBEGINy=aXORb;ENDxor2_rtl;ARCHITECTURExor_behaveOFxor2ISBEGINPROCESS(a,b)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=a&b;CASEcombISWHEN“00”=y=‘0’;WHEN“01”=y=‘1’;WHEN“10”=y=‘1’;WHEN“11”=y=‘0’;WHENOTHERS=y=‘X’;ENDCASE;ENDPROCESS;ENDxor2_behave;数据流描述行为描述第6章基本逻辑电路设计6.1.2编、译码器与选择器1.3-8译码器LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL;ENTITYdecoder3to8ISPORT(a,b,c,g1,g2a,g2b:INSTD_LOGIC;y:outstd_logic_vector(0to7));ENDdecoder3to8;ARCHITECTUREbehaveOFdecoder3to8ISSIGNALindata:STD_LOGIC_VECTOR(2DOWNTO0);BEGINindata=c&b&a;PROCESS(indata,g1,g2a,g2b)BEGINIF(g1=‘1’ANDg2a=‘0’ANDg2b=‘0’)THENCASEindataISWHEN“000”=y=“11111110”;WHEN“001”=y=“11111101”;WHEN“010”=y=“11111011”;WHEN“011”=y=“11110111”;WHEN“100”=y=“11101111”;WHEN“101”=y=“11011111”;WHEN“110”=y=“10111111”;WHEN“111”=y=“01111111”;WHENOTHERS=y=“XXXXXXXX”;ENDCASE;ELSEy=“11111111”;ENDIF;ENDPROCESS;ENDbehave;第6章基本逻辑电路设计2.优先级编码器输入输出Input(7)Input(6)Input(5)Input(4)Input(3)Input(2)Input(1)Input(0)y2y1y0XXXXXXX0111XXXXXX01110XXXXX011101XXXX0111100XXX01111011XX011111010X0111111001X1111111000常用于中断的优先级控制LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYpriorityencoderISPORT(input:INSTD_LOGIC_VECTOR(7DOWNTO0);y:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDpriorityencoder;ARCHITECTUREbehaveOFpriorityencoderISBEGINPROCESS(input)BEGINIF(input(0)=‘0’)THENy=“111”;ELSIF(input(1)=‘0’)THENy=“110”;ELSIF(input(2)=‘0’)THENy=“101”;ELSIF(input(3)=‘0’)THENy=“100”;ELSIF(input(4)=‘0’)THENy=“011”;ELSIF(input(5)=‘0’)THENy=“010”;ELSIF(input(6)=‘0’)THENy=“001”;ELSEy=“000”;ENDIF;ENDPROCESS;ENDbehave;第6章基本逻辑电路设计3.4选1选择器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux4ISPORT(input:INSTD_LOGIC_VECTOR(3DOWNTO0);a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDmux4;ARCHITECTUREbehaveOFmux4ISSIGNALsel:STD_LOGIC_VECTOR(1DOWNTO0);BEGINsel=b&a;PROCESS(input,sel)BEGINIF(sel=“00”)THENy=input(0);ELSIF(sel=“01”)THENy=input(1);ELSIF(sel=“10”)THENy=input(2);ELSEy=input(3);ENDIF;ENDPROCESS;ENDbehave;选择输入数据输入数据输出bai(0)i(1)i(2)i(3)y00aXXXa01XbXXb10XXcXcXXXXXdd第6章基本逻辑电路设计6.1.3加法器、求补器1.加法器(1)半加器输入和输出进位输出basco0000011010101101libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityhalf_adderisport(a,b:instd_logic;s,co:outstd_logic);endhalf_adder;architectureaofhalf_adderisbeginco=aandb;s=axorb;enda;只有进位输出，没有进位输入第6章基本逻辑电路设计(2)全加器输入和输出进位输出bacinsco0000001010100101100100110011011010111111libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityfull_adderisport(a,b,cin:instd_logic;s,co:outstd_logic);endfull_adder;architectureaoffull_adderissignaltemp:std_logic_vector(1downto0);beginco=(aandb)or(aandcin)or(bandcin);s=axorbxorcin;enda;第6章基本逻辑电路设计2.求补器其逻辑关系应是：最高位符号位不变，余下的位取反，然后最低位加1。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYcomplementISPORT(a:INSTD_LOGIC_VECTOR(7DOWNTO0);b:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDcomplement;ARCHITECTUREaOFcomplementISBEGINPROCESS(a)VARIABLEtemp1:STD_LOGIC;VARIABLEtemp2:STD_LOGIC_VECTOR(6DOWNTO0);VARIABLEtemp3:std_logic_vector(7downto0);BEGINIF(a(7)='0')THENb=a;ELSEtemp1:=a(7);temp2:=NOTa(6downto0);temp3:=temp1&temp2;b=temp3+1;ENDIF;ENDPROCESS;ENDa;第6章基本逻辑电路设计6.1.4三态门及总线缓冲器1.三态门LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYtri_gateISPORT(din,en:STD_LOGIC;dout:STD_LOGIC);ENDtri_gate;ARCHITECTUREaOFtri_gateISBEGINPROCESS(din,en)BEGINIF(en=‘1’)THENdout=din;ELSEdout=‘Z’;ENDIF;ENDPROCESS;ENDa;第6章基本逻辑电路设计2.单向总线缓冲器由多个三态门组成，用来驱动地址总线和控制总线。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYtri_buf8ISPORT(din:INSTD_LOGIC_VECTOR(7DOWNTO0);dout:OUTSTD_LOGIC_VECTOR(7DOWNTO0);en:INSTD_LOGIC);ENDtri_buf8;ARCHITECTUREaOFtri_buf8ISBEGINPROCESS(din,en